Wide-Multiplexer DSP Block for Concurrent Arithmetic Throughput
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing applications, such as in 3G base stations, is not adequately met by traditional DSP chips or Programmable Logic Devices (PLDs) due to bottlenecks in the PLD fabric, necessitating a more efficient digital signal processing solution.
Innovation Solution
A digital signal processing block comprising cascaded DSP elements with wide multiplexers and arithmetic logic units, configured to perform concurrent operations through programmable interconnects and logic, allowing for improved arithmetic performance by replacing multiple DSP elements with application-specific circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are configured in the programmable logic and programmable interconnect of the PLD, then concurrent DSP operations are enabled, but the fabric of the PLD becomes a bottleneck
Solution Approach 1:
The patent divides the DSP processing function into discrete, modular DSP elements that can be independently configured and cascaded. Each DSP element is a self-contained unit with dedicated multipliers and adders, allowing concurrent operations without interfering with the overall PLD fabric, thus resolving the bottleneck problem while maintaining high productivity
Solution Approach 2:
The patent introduces dedicated interconnect structures and buffer registers as intermediaries between DSP elements. These intermediaries handle data transfer and synchronization explicitly, preventing the PLD fabric from becoming a bottleneck by providing specialized pathways that do not contend with general-purpose logic resources
2Productivity
If a single DSP microprocessor is used, then the device is simple, but it cannot meet the increasing demand for more arithmetic operations per second
Solution Approach 1:
The patent merges multiple DSP elements into a unified cascaded structure where the output of one element feeds directly into the input of the next. This combining approach enables parallel arithmetic operations across multiple elements while presenting a unified interface to the rest of the system, achieving high throughput without proportionally increasing external complexity
Solution Approach 2:
The patent designs DSP elements with universal, programmable functionality that can be configured to perform different arithmetic operations. Each element contains multipliers and adders that can be programmed through the PLD configuration mechanism, allowing a single element design to serve multiple functions and reducing the need for specialized circuitry for each operation type
Data Source
AI summary
A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.