Wide Prefetch DRAM Memory Architecture with Dual-Side Amplifiers
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Solution Overview
Problem
Conventional DRAM architectures face challenges in achieving high bandwidth while maintaining low power consumption, particularly in high-performance computing applications, due to a large page size to prefetch size ratio that results in increased power consumption and access delays.
Innovation Solution
The proposed solution involves a wide prefetch (WP) DRAM architecture that doubles the global IO lines on the array, placing global amplifiers and write drivers on both sides of the array block, and routing them on the array, which increases the prefetch size and improves the page size to prefetch size ratio from 128:1 to 8:1, enhancing memory bandwidth and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM architecture with standard prefetch size is used, then device complexity is low, but memory bandwidth is limited and power consumption is high due to large page size to prefetch size ratio
Solution Approach 1:
The memory array is divided into multiple banks, and each bank is further segmented into sub-arrays with dedicated global amplifiers. This segmentation allows parallel access to multiple memory regions, effectively doubling the prefetch width and increasing memory bandwidth without proportionally increasing overall system complexity.
Solution Approach 2:
The patent introduces an additional dimension to the memory architecture by adding global amplifiers on both sides of the memory array (left and right sides), rather than only on one side. This spatial dimensionality change enables wider prefetch operations and improves bandwidth while distributing the complexity across different spatial locations.
2Productivity
If prefetch size is increased to improve bandwidth, then memory bandwidth improves, but power consumption increases due to more active circuitry
Solution Approach 1:
Data is prefetched into buffer registers in advance of actual processing needs. The wide prefetch capability allows larger amounts of data to be loaded preliminarily into local buffers, reducing the frequency of memory access operations and thereby reducing overall power consumption despite the increased prefetch width.
Solution Approach 2:
The memory system includes self-service features where locally cached data in buffers can satisfy subsequent access requests without requiring additional high-power memory operations. The architecture serves itself by utilizing previously prefetched data, reducing the need for repeated high-power access cycles.
3Quantity of substance
If global amplifiers are placed on both sides of the array block, then prefetch size doubles, but device complexity and routing complexity increase
Solution Approach 1:
The patent employs asymmetric placement of global amplifiers, with different configurations on left and right sides of the memory array. This asymmetric design allows optimization of routing paths for each side, managing complexity by tailoring the configuration to specific performance requirements rather than using a symmetric design that would require identical complex routing on both sides.
4Use of energy by moving object
If page size to prefetch size ratio is reduced from 128:1 to 8:1, then power consumption decreases, but requires significant architectural changes
Solution Approach 1:
The patent fundamentally changes the architectural parameters of the memory system by doubling the prefetch width and modifying the global amplifier configuration. These parameter changes enable the reduction of the page size to prefetch size ratio from 128:1 to 8:1, achieving lower power consumption through more efficient data transfer and reduced access operations.
Data Source
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Figure 3A
Figure 3B~4
AI summary
An embodiment of an electronic apparatus may include a silicon substrate and a memory circuit coupled to the silicon substrate, the memory circuit including an array block of memory tiles coupled to the silicon substrate, a first set of global amplifiers coupled to the silicon substrate and the memory tiles and arranged along a first side of the array block, a first set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the first side of the array block, a second set of global amplifiers coupled to the silicon substrate and coupled to the memory tiles and arranged along a second side of the array block opposite to the first side of the array block, and a second set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the second side of the array block. Other embodiments are disclosed and claimed.