Wide-Range IO Transceiver Switching for Glitch-Free Mode Transitions
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Solution Overview
Problem
Designing IO circuits for integrated circuits that can accommodate multiple IO standards across a wide supply range is challenging due to glitches occurring during mode transitions between high-voltage and low-voltage modes, caused by mismatched delay in data paths.
Innovation Solution
A glitch-free wide supply range transceiver is developed, utilizing a transmitter with level-shifters, pre-drivers, and a driver configuration that includes stacks of p-channel and n-channel transistors, along with a control circuit to manage voltage swings and bias voltages, ensuring smooth operation without glitches during mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two different data paths are used to drive the IO pad in high- and low-voltage modes, then the IO circuit can accommodate multiple IO standards across a wide supply range, but glitches occur at the IO pad and at the output of the receivers when switching from one mode to the other mode
Solution Approach 1:
The patent applies preliminary action by introducing a delay element that delays the enable signal to the second data path. This delay is configured to match the turn-on delay of the first data path, ensuring that both data paths are activated simultaneously during mode transitions. By pre-synchronizing the activation timing of both paths, the patent eliminates glitches that would otherwise occur due to mismatched delay, thereby resolving the contradiction between supporting multiple IO standards and maintaining glitch-free operation.
2Adaptability or versatility
If two different receivers are used to receive data from the IO pad in high- and low-voltage modes, then the receiver can handle multiple voltage modes, but glitches occur at the IO pad and at the output of the receivers when there is switching from one mode to the other mode
Solution Approach 1:
The patent applies preliminary action by delaying the enable signal to the second receiver through a delay element. This delay is carefully configured to match the turn-on delay of the first receiver, ensuring that both receivers are activated simultaneously during mode transitions. By pre-synchronizing the activation timing, the patent prevents glitches at the receiver output that would otherwise result from mismatched delay characteristics, thus resolving the contradiction between multi-mode reception capability and glitch-free operation.
3Reliability
If a single data path is used for both high- and low-voltage modes, then mode switching glitches are eliminated, but the IO circuit cannot accommodate multiple IO standards across a wide supply range
Solution Approach 1:
The patent applies segmentation by dividing the data path into two separate data paths, each optimized for specific voltage modes. The first data path is optimized for high-voltage modes while the second data path is optimized for low-voltage modes. By segmenting the data path in this manner, the patent enables the IO circuit to accommodate multiple IO standards across a wide supply range while maintaining optimal performance in each mode. The segmentation is complemented by synchronized switching control to eliminate glitches.
Solution Approach 2:
The patent introduces an intermediary delay element that mediates the switching between the two segmented data paths. This delay element acts as a buffer that synchronizes the activation of both data paths during mode transitions, ensuring smooth handover without glitches. The intermediary component enables the system to benefit from both segmented data paths (for adaptability) and synchronized switching (for reliability).
Data Source
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AI summary
An example receiver includes: a pad splitter circuit (304) coupled to a pad (302), the pad splitter circuit configured to generate a first logic signal (pad_top) and a second logic signal (pad_bot); a wide-range receiver (306) coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger (306HV) receiver and a second Schmitt trigger receiver (306HV); a control circuit (312) coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit (308) coupled to the pad splitter circuit and the wide-range receiver.