Wide-Voltage Gate Driver with Clamped Low-Oxide Transistors
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Solution Overview
Problem
Semiconductor processes produce transistors with limited gate oxide voltage ratings, limiting the output voltage that gate drivers can achieve, and existing gate drivers require large pass-transistors to generate sufficient current, especially at lower supply voltages, leading to inadequate performance.
Innovation Solution
A gate driver circuit using first, second, and third transistors, along with voltage clamps and control logic, ensures that the transistors operate within safe voltage limits by rapidly turning on and maintaining them in an on-state, utilizing dual-knee clamps to protect against excessive gate-to-source voltage and reducing quiescent current through controlled current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors with thin gate oxide layers are used to reduce device size and improve integration, then device density and manufacturing efficiency are improved, but the maximum gate-to-source voltage rating is reduced, limiting the output voltage capability of gate drivers
Solution Approach 1:
The patent introduces an intermediary voltage clamp circuit that mediates between the high-voltage output requirement and the low-voltage transistor gate oxide limitation. The clamp circuit actively regulates the gate-to-source voltage to prevent exceeding the thin oxide rating while enabling the transistor to switch higher voltage loads, thus resolving the contradiction between device integration and voltage handling capability.
Solution Approach 2:
The patent dynamically changes the operating parameters of the transistor by using adaptive gate driving with voltage clamping. The gate-to-source voltage is adjusted in real-time based on the switching state and load conditions, allowing the transistor to operate safely within its reduced voltage rating while still controlling higher voltage circuits through the gate driver's voltage multiplication capability.
2Power
If large pass-transistors are used to generate sufficient current at lower supply voltages, then current delivery capability is improved, but device area and circuit complexity increase
Solution Approach 1:
The patent employs dynamic current boosting through adaptive gate driving where the gate voltage is temporarily elevated above the steady-state level during switching transitions. This dynamic voltage enhancement provides additional current drive capability during critical switching periods without requiring permanently larger transistors, thus maintaining power performance while reducing device area.
Solution Approach 2:
The patent uses periodic voltage clamping and adaptive gate driving pulses to deliver high current only when needed during switching events. Rather than maintaining continuously high current capability through large transistor sizes, the circuit periodically applies voltage boosts synchronized with the switching frequency, achieving equivalent current delivery with smaller devices.
3Reliability
If voltage clamps are added to protect transistors from excessive gate-to-source voltage, then transistor reliability is improved, but circuit complexity and component count increase
Solution Approach 1:
The patent merges the voltage clamp functionality with the gate driver output stage by integrating the clamp transistors and control logic into the existing gate driver architecture. Rather than adding separate protection circuits, the clamp function is combined with the driving function, sharing common transistors and control signals, thus providing protection while minimizing additional complexity.
Solution Approach 2:
The patent designs the gate driver circuit with multi-functional transistors that serve both as switching elements and as voltage clamp components. The same transistors and control logic perform multiple functions including current switching, voltage regulation, and overvoltage protection, thereby improving reliability without proportionally increasing circuit complexity.
Data Source
Figure 1~4
Figure 2
Figure 5~6
AI summary
A gate driver circuit includes first through third transistors (M1, M3, M4), a first voltage clamp (206), and control logic (210). The first transistor (M1) has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp (206) couples between the first voltage terminal and the first control input. The second transistor (M3) couples between the first control input and the second voltage terminal. The third transistor (M4) couples between the first control input and the second voltage terminal. The third transistor (M4) is smaller than the second transistor (M3). The control logic (210) is configured to turn on both the second and third transistors (M3 and M4) to thereby turn on the first transistor (M1), and the first control logic (210) is configured to turn off the second transistor (M3) after the first transistor (M1) turns on while maintaining in an on-state the third transistor (M4) to maintain the first transistor (Ml) in the on-state.