Wide-Voltage Gate Driver With Vgs Clamp for Thin-Oxide Transistors
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Solution Overview
Problem
Existing gate driver circuits face challenges in producing output voltages higher than the maximum Vgs rating of transistors, particularly in applications requiring 7V or higher, such as buck converters and motor controllers, where the transistors have limited Vgs voltage ratings due to thin gate oxide layers.
Innovation Solution
The proposed gate driver circuit includes first, second, and third transistors, a first voltage clamp, and control logic. The control logic turns on both the second and third transistors to turn on the first transistor, then turns off the second transistor while maintaining the third transistor on to maintain the first transistor in an on-state, ensuring the Vgs of the transistors does not exceed safe operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate driver circuit uses transistors with thin gate oxide layers to achieve higher switching speeds and lower on-resistance, then the transistor performance is improved, but the maximum Vgs rating is reduced below the required output voltage level
Solution Approach 1:
The gate driver circuit is segmented into multiple transistor stages (first transistor, second transistor, third transistor) with different functions. The second and third transistors form a push-pull configuration that can generate high output voltages, while the first transistor with thin gate oxide provides high switching performance. This segmentation allows each transistor to operate within its safe voltage limits while achieving the required high output voltage capability.
Solution Approach 2:
The first transistor acts as an intermediary between the control logic and the high-voltage output stage. It is controlled by the second and third transistors which generate the appropriate gate voltages. This intermediary structure allows the high-performance thin-oxide first transistor to be driven without directly exposing it to the full output voltage stress.
2Power
If the gate driver circuit generates output voltages higher than 5V to meet application requirements, then the voltage capability is improved, but the transistor gate oxide layers are at risk of breakdown
Solution Approach 1:
The gate driver employs dynamic control of the second and third transistors to generate time-varying gate voltages for the first transistor. During switching transitions, the voltages dynamically rise and fall to achieve the required high output voltage capability. The control logic dynamically adjusts the voltage levels to ensure they never exceed the safe Vgs rating during steady-state operation while still achieving high voltage output during switching events.
Solution Approach 2:
The second and third transistors operate in a periodic push-pull manner to charge and discharge the gate of the first transistor. This periodic action generates the necessary high-voltage output waveform while keeping the average voltage stress on any single transistor within safe limits. The alternating operation ensures that no single transistor is continuously exposed to maximum voltage stress.
3Power
If the gate driver circuit uses a single large transistor to provide high current capability, then the current output is improved, but the transistor size and device complexity increase
Solution Approach 1:
The current output capability is achieved by segmenting the transistor structure into three smaller transistors rather than using one large transistor. The second and third transistors work together in a push-pull configuration to drive the first transistor, providing high current capability through coordinated operation of multiple smaller devices. This segmentation reduces the physical size of each individual transistor while maintaining overall high current output capability.
Solution Approach 2:
The second and third transistors are merged in a push-pull configuration where their combined action provides the high current drive capability. By merging their output currents at the gate of the first transistor, the circuit achieves high current output capability that would require a much larger single transistor, while keeping individual device sizes manageable and overall complexity controlled.
Data Source
AI summary
A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.