Wideband Buffer Circuit With Low Output Impedance and High Linearity
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Solution Overview
Problem
Existing buffer circuits struggle to maintain high linearity over a wide range of input signal powers and frequencies when driving a low impedance load, often requiring additional stages to convert differential signals to single-ended outputs, which increases power consumption and complexity.
Innovation Solution
A wideband highly-linear buffer circuit design that includes a first signal transistor, a second signal transistor, a third signal transistor, and a current source, with specific bias circuits for AC and DC coupling, allowing the circuit to efficiently convert differential signals to single-ended outputs with low output impedance and high linearity across a wide frequency band and power range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a common drain circuit (source follower) is used to drive a low impedance load, then the output impedance is low, but the circuit can only receive single-ended signals requiring an additional preceding stage to convert differential signals
Solution Approach 1:
The patent combines the differential to single-ended conversion function and the buffer driving function into a single integrated circuit stage. The first transistor converts the differential signal while the second transistor simultaneously provides the buffer output drive, eliminating the need for separate conversion and buffering stages.
Solution Approach 2:
The circuit performs multiple functions in a single stage: it converts differential signals to single-ended signals, provides low output impedance for driving low impedance loads, and maintains high linearity. This multi-functional design eliminates the need for additional preceding stages.
2Reliability
If multiple amplifier stages are employed to achieve desired buffer characteristics, then linearity and output impedance improve, but power consumption and circuit complexity increase
Solution Approach 1:
The patent merges the signal conversion and buffering functions into one stage, avoiding the need for multiple amplifier stages. This single-stage design achieves the desired linearity and output impedance characteristics without the cumulative power consumption of multiple stages.
Solution Approach 2:
The circuit uses biasing circuits to optimize the operating parameters of the transistors, achieving high linearity and low output impedance through proper parameter selection rather than through multiple amplification stages.
3Stability of the object's composition
If a super source follower circuit is used to reduce output impedance, then output impedance decreases, but the circuit still requires a preceding differential to single-ended conversion stage
Solution Approach 1:
The patent integrates the differential to single-ended conversion with the super source follower buffer in a single circuit stage. The first transistor handles the differential conversion while the second transistor provides the super source follower buffering action, eliminating the need for a separate conversion stage.
4Adaptability or versatility
If the buffer circuit is designed for wideband operation, then frequency range increases, but maintaining high linearity across the entire band becomes difficult
Solution Approach 1:
The circuit employs biasing circuits that can be designed to maintain optimal transistor operating parameters across a wide frequency range. By carefully selecting biasing components and transistor parameters, the circuit maintains high linearity throughout the entire operating band.
Data Source
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Figure 6A~7
AI summary
A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.