Wideband DAC Load Attenuator for Low-Power High-Resolution Output

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Solution Overview

Problem

Existing wideband digital to analog converters (DACs) face challenges in achieving low power consumption while maintaining high resolution and wide bandwidth, making them unsuitable for battery-operated wireless communication devices due to high power dissipation and limited dynamic performance.

Innovation Solution

A wideband DAC with a built-in load attenuator, utilizing a double cascaded current source and differential current-mode switch, along with a direct current offset stage, to reduce power consumption and improve dynamic performance by minimizing signal/code-dependent behavior and enabling fast discharge of glitch energy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If existing wideband DAC designs are used to achieve high resolution and wide bandwidth, then conversion performance is improved, but power consumption increases making them unsuitable for battery-operated devices

Engineering Contradiction:
Improveconversion resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent divides the DAC architecture into multiple independent segments: a first DAC core for baseband signal conversion, a second DAC core for RF signal conversion, and separate current source circuits for each. This segmentation allows each segment to operate independently at optimized power levels, enabling the system to achieve wideband performance through coordinated operation of multiple lower-power units rather than requiring a single high-power wideband DAC.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic power management by enabling or disabling specific DAC cores and current sources based on operating conditions. The controller can activate only the necessary DAC core (first for baseband, second for RF) depending on the signal type being processed, and dynamically adjust current source outputs to match instantaneous signal requirements, thereby reducing average power consumption while maintaining peak performance when needed.

Inventive Principle:
Principle #15Dynamics

2Reliability

If DAC operating current is increased to improve dynamic performance, then signal quality is improved, but power dissipation increases

Engineering Contradiction:
Improvedynamic performanceVSAvoidpower dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent employs periodic switching of current sources and DAC cores based on signal requirements. Instead of maintaining high current continuously, the system activates high-current modes only when wideband RF signals are being processed, and switches to low-current baseband mode otherwise. This periodic activation of high-performance modes achieves the necessary dynamic performance for signal quality while dramatically reducing average power dissipation during baseband-only operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent dynamically changes operating parameters including current source output levels, DAC core activation states, and switching frequencies based on the type of signal being processed. For baseband signals, the system uses lower current levels and disables the RF DAC core, while for RF signals it activates the second current source and second DAC core at higher current levels, thereby optimizing the balance between dynamic performance and power dissipation for each operating condition.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If wideband operation is implemented to support higher data rates, then communication capacity is improved, but power consumption and complexity increase

Engineering Contradiction:
Improvedata rateVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent creates a multi-functional DAC system where two DAC cores can operate independently or in coordination to handle different signal types (baseband and RF). The shared current sources and control logic provide universal functionality that adapts to various operating modes: baseband-only operation using the first DAC core, RF operation using the second DAC core, or combined operation for wideband applications. This universality allows the system to achieve wideband data rates when needed while falling back to lower-power narrowband modes for standard operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Manufacturing precision

If multiple current sources are used to reduce signal/code-dependent behavior, then linearity is improved, but device complexity increases

Engineering Contradiction:
ImprovelinearityVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the current sourcing function into multiple independent current sources, each dedicated to specific DAC cores. The first current source circuit serves the first DAC core for baseband operation, while the second current source circuit serves the second DAC core for RF operation. This segmentation allows each current source to be optimized for its specific function, improving linearity by reducing signal/code-dependent variations, while the modular structure keeps complexity manageable through functional separation rather than requiring a single complex current source.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8169353B2Wideband digital to analog converter with built-in load attenuator
Publication Date: 2012.05.01 QUALCOMM INC
  • US8169353B2 patent drawing
  • US8169353B2 patent drawing
  • US8169353B2 patent drawing

AI summary

A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.