Widened Backside Source/Drain Contacts for Scaled Nanowire ICs
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of multi-gate transistors to the 10 nanometer node or sub-10 nanometer range, leading to challenges in integrating new technologies and optimizing device performance, particularly in bulk silicon substrates.
Innovation Solution
The implementation of direct backside source or drain contacts through increased process margin and controlled gate depth, utilizing techniques such as backside gate recess and selective etching to reduce parasitic capacitance and enable efficient power delivery, while maintaining distance from transistor gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistors, then existing bulk silicon substrate infrastructure can be utilized, but process variability limits scalability to 10 nanometer node or sub-10 nanometer range
Solution Approach 1:
The patent introduces backside contacts as a new dimensional approach to transistor fabrication. Instead of only front-side processing, the method accesses the substrate from the backside to form contacts, enabling new process flows that achieve the required precision for 10nm and sub-10nm nodes while maintaining compatibility with bulk silicon substrates
Solution Approach 2:
The patent employs parameter changes including selective etching depths, controlled gate recess dimensions, and adjusted contact formation parameters. These parameter optimizations enable precise control over transistor characteristics at scaled dimensions, reducing process variability while maintaining manufacturing feasibility
2Object-generated harmful factors
If direct backside source or drain contacts are implemented, then parasitic capacitance is reduced and power delivery is improved, but fabrication process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the backside contacts and adjusting gate depths before final transistor assembly. The gate recess and contact formation are executed in advance, allowing subsequent processing steps to proceed more smoothly and reducing overall process complexity despite the added backside access requirement
Solution Approach 2:
The patent introduces intermediary structures and process steps, such as sacrificial layers and controlled etch stop points, that mediate between the backside contact formation and the final transistor structure. These intermediaries enable precise control over contact depth and gate positioning, reducing parasitic capacitance while managing fabrication complexity
3Power
If gate depth is increased to enable direct backside contacts, then power delivery efficiency improves, but distance from transistor gates increases reducing control
Solution Approach 1:
The patent applies local quality by creating non-uniform gate structures with varying depths in different regions. The gate recess is selectively applied where backside contacts are formed, allowing optimal power delivery in those locations while maintaining adequate gate control. This localized modification enables simultaneous optimization of both power efficiency and gate control
Data Source
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AI summary
Integrated circuit structures having direct backside source or drain contacts are described. An integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the first epitaxial source or drain structure without laterally overlapping with the first gate stack or the second gate stack. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin.