Wider DLD Metal Pads for Lower-Resistance Die Interconnects
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in reducing signal path resistance and improving conductivity between die interconnects and metal pads due to limitations in metallization layer design, particularly during the chemical mechanical polishing (CMP) process which can cause dimpling and increase resistivity.
Innovation Solution
The implementation of a die level distribution (DLD) metallization layer with metal pads having a width greater than the metal lines, fabricated using conventional dual damascene processes, to enhance conductivity by tolerating some dimpling and increasing the surface area for better coupling with larger die interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal pad width is increased to support larger die interconnects and improve conductivity, then the signal path conductivity is improved, but the chemical mechanical polishing (CMP) process causes dimpling on the metal pad surface which increases resistivity
Solution Approach 1:
The patent changes the dimensional parameter of the metal pad by making its width greater than the width of the metal line. This parameter change allows the metal pad to support larger die interconnects while the increased surface area compensates for the resistivity increase caused by CMP-induced dimpling, thereby maintaining or improving overall signal path conductivity
Solution Approach 2:
The patent applies partial excessive action by intentionally allowing some dimpling on the metal pad surface during CMP processing. Rather than preventing all surface irregularities, the design tolerates a controlled amount of dimpling while relying on the increased metal pad width to provide sufficient conductivity, recognizing that the benefit of larger contact area outweighs the harm of minor surface imperfections
2Ease of manufacture
If conventional dual damascene processes are used to fabricate the DLD metallization layer, then the manufacturing complexity is reduced, but the metal pad surface suffers from dimpling which impacts resistivity
Solution Approach 1:
The patent modifies the geometric parameter of the metal pad by extending its width beyond the metal line width. This dimensional adjustment compensates for the resistivity increase caused by CMP dimpling, allowing the use of conventional dual damascene processes without sacrificing electrical performance
Solution Approach 2:
The patent converts the harmful effect of CMP-induced dimpling into a beneficial outcome by designing wider metal pads. The increased surface area from the extended pad width provides additional conductive pathways that compensate for and overcome the resistivity increase from surface dimpling, effectively transforming a manufacturing defect into an acceptable trade-off
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves signal path conductivity by outweighing the resistivity increase from dimpling with the gain in conductivity from the increased surface area of wider metal pads, supporting larger die interconnects for enhanced electrical and mechanical coupling.
Implementation Method 1
The DLD metallization structure is fabricated utilizing conventional dual damascene processes which include a polishing step, such as a chemical mechanical polishing (CMP), to fabricate a smooth coupling surface of the metal pads to die interconnects.
Implementation Method 2
The metal pads have a width that is greater than the width of the metal lines formed in the DLD metallization layer... The wider metal pads thus electrically and mechanically support correspondingly larger die interconnects for improved signal path conductivity therebetween.
Data Source
AI summary
A semiconductor die having a die interconnect and a die level distribution (DLD) metallization layer having a metal line and a metal pad having a width greater than the width of the metal line to support a larger die interconnect for improved signal path conductivity between the die interconnect and the metal pad is disclosed. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The die includes a semiconductor layer, a DLD metallization structure, and a back end of line (BEOL) interconnect structure between the semiconductor layer and the DLD metallization structure. The DLD metallization structure mechanically supports die interconnects for coupling the die to another device, such as a package substrate or another die, and redistributes signals (e.g., power, ground, information) between the die interconnects and the semiconductor layer through the BEOL interconnect structure.