Wider Vias in Integrated Passive Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges in manufacturing complex passive components due to limitations in sub-micron vias for connecting metal layers, which restrict the use of thick metal and high conductivity metals, leading to high costs and limited area efficiency for passive circuitry.
Innovation Solution
The implementation of vias with widths greater than the conductive traces in integrated passive devices, allowing for electrical connection between conductive traces, enables the use of coarse process constraints and thick metal/thick dielectric layers, facilitating the manufacture of complex passive components with high Q factors and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sub-micron vias are used to connect metal layers, then manufacturing precision is improved, but device complexity increases and area efficiency decreases
Solution Approach 1:
The patent changes the via width parameter from sub-micron to greater than the conductive trace width, enabling the use of coarse process constraints instead of precise sub-micron processes. This parameter change simplifies the manufacturing process while maintaining electrical connection functionality.
Solution Approach 2:
Instead of making the via smaller than the trace (conventional approach), the patent inverts the approach by making the via wider than the trace. This inversion allows the via to enclose and connect to the trace more easily, reducing manufacturing complexity.
2Manufacturing precision
If sub-micron vias are used to connect metal layers, then manufacturing precision is improved, but area efficiency worsens
Solution Approach 1:
By changing the via width parameter to be greater than the trace width, the patent enables coarse process constraints that reduce the overall area required for passive components while maintaining electrical connection functionality.
3Reliability
If thick metal layers are used for passive components, then electrical performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent changes the via width parameter to enable coarse process constraints, which simplifies the manufacturing of thick metal layers. The wider via allows for less precise alignment and easier fabrication of thick conductive traces used in passive components.
4Ease of manufacture
If coarse process constraints are used, then manufacturing cost is reduced, but manufacturing precision worsens
Solution Approach 1:
The patent inverts the conventional approach by making the via wider than the trace, which compensates for the reduced precision of coarse processes. The larger via dimension provides tolerance for dimensional variations inherent in coarse manufacturing processes.
Solution Approach 2:
The via structure is designed to enclose the conductive trace, creating a segmented connection approach that maintains electrical connection reliability even with coarse manufacturing precision.
Data Source
AI summary
This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.