WiFi SoC Memory Power Minimization via Segmented Banks
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Solution Overview
Problem
The power consumption of WiFi client systems during idle periods is high due to the need to maintain memory contents, especially in DTIM Mode where the system listens to every Nth beacon, with memory leakage contributing significantly to overall power consumption, and existing solutions like burning code into ROM or using secondary memory have limitations such as immutability and security risks.
Innovation Solution
A holistic architecture for the WiFi SoC that includes independently powered memory banks, a Memory Management Unit (MMU) for demand paging, and a communications bus to fetch pages from host memory without waking the host processor, allowing for dynamic power management and secure access to code/data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the WiFi client maintains memory contents during idle periods, then the processor can quickly resume operation, but power consumption increases due to memory leakage current
Solution Approach 1:
The memory system is divided into multiple independently controllable memory banks. Each bank can be individually powered on or off based on whether its contents are needed, allowing selective retention of only necessary data while powering down others to eliminate leakage current from unused memory segments.
Solution Approach 2:
The system performs preliminary identification of which memory banks contain data needed for upcoming operations before entering idle mode. This allows proactive powering down of unnecessary banks while keeping essential banks active, preparing the system for low-power operation in advance.
2Use of energy by moving object
If code is burned into ROM memory, then power consumption decreases, but the system loses adaptability for updating code and adding new features
Solution Approach 1:
The system transitions from static ROM to dynamic RAM-based storage with intelligent power management. Memory contents are dynamically retained only when needed, and banks are selectively powered down when not in use, providing both low-power operation and full adaptability for code updates and feature additions.
Solution Approach 2:
The system changes the power state parameter of memory banks dynamically based on usage requirements. By controlling the power parameter individually for each bank, the system achieves low power consumption during idle periods while maintaining the ability to load and update code as needed.
3Reliability
If the system listens to every beacon, then network awareness is maintained, but power consumption increases
Solution Approach 1:
The system transitions from continuous beacon listening to periodic sampling by listening to every Nth beacon. This periodic approach maintains sufficient network awareness while significantly reducing the duty cycle of the RF receiver and associated processing, thereby lowering power consumption during idle periods.
4Use of energy by moving object
If secondary memory is used to store code, then power consumption decreases, but security risks increase due to potential unauthorized access
Solution Approach 1:
The system extracts and isolates critical code and data into dedicated, protected memory banks that can be securely powered on only when needed. This separation allows the system to use low-power secondary storage for bulk data while maintaining security for essential operations through controlled access to specific memory regions.
Data Source
AI summary
The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.