Wi-Fi TSF Clock Synchronization for Audio Buffer Stability
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Solution Overview
Problem
The unsynchronized system clocks in a wireless Wi-Fi link between a dongle transmitter and receiver cause buffer overflow or underflow, which disrupts the transmission of high-quality audio and video signals in a wireless one connected line (WOCL) solution.
Innovation Solution
A method for clock synchronization between a transmitter and receiver involves sampling multiple timestamps and TSF timestamps using a Wi-Fi timing synchronization function, generating initial and target phase differences, and performing coarse and fine tunes to adjust the receiver system clock frequency, ensuring synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a wireless Wi-Fi link is used to replace HDMI cable for audio and video transmission, then installation flexibility and wireless convenience are improved, but clock synchronization between transmitter and receiver deteriorates, causing buffer overflow or underflow
Solution Approach 1:
The patent introduces a timing synchronization function (TSF) as an intermediary mechanism between the transmitter and receiver clocks. The TSF provides a reference timestamp that both sides use to calculate their respective clock offsets, enabling indirect synchronization without requiring direct clock coupling or complex handshake protocols.
Solution Approach 2:
The system implements feedback by having the receiver calculate its clock offset relative to the transmitter based on received timestamps, then adjust its local clock frequency accordingly. This closed-loop feedback mechanism continuously corrects drift and maintains synchronization over time.
2Measurement precision
If multiple timestamps are sampled and processed to achieve clock synchronization, then clock synchronization accuracy is improved, but computational complexity and processing time increase
Solution Approach 1:
The synchronization process is segmented into distinct phases: timestamp collection, offset calculation, and clock adjustment. By dividing the complex synchronization task into manageable segments, the system can process timestamps systematically without overwhelming computational burden.
Solution Approach 2:
The patent samples multiple timestamps (more than the minimum single pair) to calculate clock offset. This excessive sampling provides redundancy and improves measurement accuracy through statistical processing, while the calculations remain tractable because they operate on simple timestamp differences rather than complex signal analysis.
Data Source
AI summary
A method of clock synchronization between a transmitter and a receiver includes sampling a first receiver timestamp and a second receiver timestamp of the receiver at a first time and a second time respectively, sampling a first transmitter timestamp and a second transmitter timestamp of the transmitter at a third time and a fourth time respectively, sampling a first timing synchronization function (TSF) receiver timestamp and a second TSF receiver timestamp by a Wi-Fi TSF at the first time and the second time respectively, sampling a first TSF transmitter timestamp and a second TSF transmitter timestamp by the Wi-Fi TSF at the third time and the fourth time respectively, generating an initial timestamp, generating an initial TSF timestamp, generating a target phase difference, and performing a coarse tune at a receiver system clock periodically to compensate the target phase difference.