WiFi 7 Demapper Structure for Low-Complexity 4096-QAM Detection
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Solution Overview
Problem
The evolution of WiFi standards to 802.11be (WiFi 7) requires higher frequency, complexity, and power consumption, posing challenges for signal transmission and reception, particularly in supporting high-throughput applications like augmented and virtual reality, where existing hardware structures are inadequate.
Innovation Solution
A signal transmission and reception apparatus with a simplified demapper structure, utilizing a transceiver to demodulate signals, calculate status data, and estimate bit information using zero-forcing and squaring channel estimation values, while avoiding complex division operations to reduce hardware complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional demapper structures are used to support WiFi 7 standards, then signal transmission capability is improved, but hardware complexity increases
Solution Approach 1:
The demapper is divided into multiple processing units including a zero-forcing processing unit, a squaring processing unit, and a subtraction processing unit. Each unit handles specific computational tasks independently, enabling parallel processing of signal data while maintaining modular hardware architecture that reduces overall system complexity.
Solution Approach 2:
Complex division operations in the demapper are replaced with computationally simpler operations including zero-forcing (multiplication by conjugate), squaring, and subtraction. This substitution maintains signal processing accuracy while significantly reducing hardware complexity and computational burden.
2Productivity
If conventional demapper structures are used to support WiFi 7 standards, then signal transmission capability is improved, but power consumption increases
Solution Approach 1:
The patent replaces computationally intensive division operations with simpler arithmetic operations (zero-forcing, squaring, subtraction) that require fewer computational cycles and less energy. This substitution maintains demapping accuracy while reducing power consumption in the signal processing chain.
Solution Approach 2:
By segmenting the demapper into specialized processing units, the patent enables efficient resource utilization and reduces redundant computations. Each processing unit is optimized for specific operations, minimizing overall power consumption while maintaining high throughput capability.
3Productivity
If high-order modulation (4096-QAM) is used to increase throughput, then data transmission rate is improved, but signal detection accuracy deteriorates
Solution Approach 1:
The patent employs zero-forcing processing that uses channel state information to pre-compensate for channel effects before detection. By replacing complex division-based equalization with zero-forcing multiplication followed by squaring and subtraction operations, the system achieves accurate signal detection even in high-order 4096-QAM modulation where signal points are densely packed.
Data Source
AI summary
An apparatus for transmitting and receiving signal may include a transceiver configured to receive a reception signal through a channel and demodulate the reception signal into a reception symbol and a channel estimation value corresponding to the reception signal, and a demapper configured to detect a modulation type of the reception signal, calculate a first status data based on a first value obtained by zero-forcing the reception symbol and a second value obtained by squaring the channel estimation value, calculate a second status data based on the second value, and estimate bit information with respect to the reception symbol based on the modulation type, the first status data, and the second status data.