Wimpy Transistor Stack Isolation for Lower Leakage Current
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Solution Overview
Problem
Existing integrated circuit devices face challenges in reducing leakage current and power consumption, particularly in multi-channel transistor structures where process complexity is high and channel width modifications are restricted.
Innovation Solution
The implementation of a wimpy transistor stack in an integrated circuit device, where the wimpy transistor stack comprises upper and lower transistors with vertically stacked channel regions and source/drain regions, along with a source/drain isolation layer that electrically isolates certain channel regions to reduce current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-channel transistor structure is used to increase integration density, then the integration density is improved, but the leakage current increases
Solution Approach 1:
The transistor stack is divided into multiple channel regions (first upper channel region, second upper channel region, first lower channel region, second lower channel region) separated by isolation layers. This segmentation allows selective electrical isolation of individual channel regions, enabling reduced leakage current in non-critical channels while maintaining functionality in critical channels, thus resolving the contradiction between high integration density and leakage current reduction.
Solution Approach 2:
Different channel regions are assigned different electrical isolation characteristics. Some channel regions are fully electrically isolated from source/drain regions while others maintain electrical connection. This local differentiation of electrical properties allows the device to achieve both high integration density through multi-channel structure and reduced leakage current through selective isolation of specific channel regions.
2Loss of energy
If channel width is modified to reduce leakage current, then the leakage current is reduced, but the process complexity increases
Solution Approach 1:
Instead of modifying channel width in the lateral dimension to control leakage, the patent uses vertical stacking to create multiple channel regions separated by isolation layers. This dimensional transition from lateral to vertical control enables leakage current reduction through electrical isolation in the vertical direction, avoiding the need for complex lateral channel width modifications and associated process complexity.
3Loss of energy
If channel width is modified to reduce leakage current, then the leakage current is reduced, but the design constraints are increased
Solution Approach 1:
The transistor is segmented into multiple independently controllable channel regions with different electrical isolation states. This segmentation provides design flexibility by allowing selective isolation of channel regions based on circuit requirements, enabling adaptation to different design scenarios without being constrained by fixed channel width modifications.
Data Source
AI summary
An integrated circuit device includes a wimpy transistor stack on a substrate, wherein the wimpy transistor stack comprises: an upper transistor comprising: a plurality of upper channel regions stacked in a vertical direction; and an upper source/drain region that contacts at least one of the plurality of upper channel regions; a lower transistor that is between the substrate and the upper transistor and comprises: a plurality of lower channel regions stacked in the vertical direction; and a lower source/drain region that contacts at least one of the plurality of lower channel regions; and a source/drain isolation layer separating the upper source/drain region from the lower source/drain region, wherein the source/drain isolation layer contacts a lowermost one of the plurality of upper channel regions and/or an uppermost one of the plurality of lower channel regions.