Wimpy Vertical Transistor Dipole Liners for Leakage Control
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Solution Overview
Problem
Fabricating wimpy vertical transistors with different gate lengths alongside standard vertical transistors is challenging due to topography issues, as wimpy vertical transistors are shorter, making it difficult to maintain distinct threshold voltages and reduce chip power consumption in non-critical circuit paths.
Innovation Solution
The use of bi-layer dipole liners in spacers to extend the effective gate length and adjust the electric field near source drain regions, allowing for the formation of wimpy vertical transistors with longer gate lengths and lower voltage leakage by incorporating a first layer of silicon oxide and a second layer of silicon nitride or aluminum oxide within the spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If wimpy vertical transistors are made with shorter gate lengths, then chip power consumption is reduced, but threshold voltage control becomes difficult and leakage increases
Solution Approach 1:
The dipole liner is applied locally at the source/drain regions adjacent to the gate, creating a localized electric field modification zone. This allows the channel region to maintain proper threshold voltage control while the source/drain interface benefits from reduced leakage through the dipole-induced field effect.
Solution Approach 2:
The dipole liner comprises a composite structure with a first liner material (e.g., silicon oxide) and a second liner material (e.g., silicon nitride or aluminum oxide) with different dielectric properties. This composite structure creates a dipole moment at the interface, generating an electric field that suppresses leakage current while maintaining threshold voltage control.
2Adaptability or versatility
If wimpy vertical transistors are fabricated alongside standard transistors, then circuit performance is optimized, but topography issues arise due to height differences
Solution Approach 1:
The dipole liner is selectively formed only in the wimpy transistor regions, allowing these devices to achieve longer effective gate lengths and proper threshold voltage control without requiring physical modifications to the standard transistor structures. This localized approach maintains topography uniformity across the wafer while enabling performance optimization for specific circuit paths.
3Reliability
If larger gate lengths are used in wimpy devices, then threshold voltage is increased and leakage is reduced, but device area increases
Solution Approach 1:
The dipole liner acts as an intermediary structure that modifies the electric field at the source/drain-gate interface. By introducing this intermediate layer with specific dielectric properties, the effective gate length is extended without physically increasing the gate structure dimensions, thereby reducing leakage current while maintaining compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of wimpy vertical transistors with longer effective gate lengths, achieving the desired threshold voltage adjustments and reducing leakage, thus facilitating their integration alongside standard transistors without compromising circuit performance.
Implementation Method 1
bi-layer dipole liners in spacers to extend the effective gate length and adjust the electric field near source drain regions
Implementation Method 2
a first layer of silicon oxide and a second layer of silicon nitride or aluminum oxide within the spacers
Data Source
AI summary
A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.