Self-Tracking Window ADC with Dynamic Delay-Line Ranging
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Solution Overview
Problem
Conventional delay line analog-to-digital converters (ADCs) face challenges in achieving high bit resolution while minimizing complexity, footprint, and current consumption, as the number of detection units and sampling latches increases with bit resolution, leading to higher complexity, wiring, and power consumption.
Innovation Solution
The proposed solution involves a delay line ADC architecture with a first and second delay line, where the delay units are controlled by respective signals, and a pulse generator aligns pulse timings by adjusting the delay of the second group of delay units through selective bypassing, allowing for a reduced sampling window and dynamic bit resolution adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of detection units and sampling latches is increased to achieve high bit resolution, then measurement precision is improved, but device complexity and current consumption increase
Solution Approach 1:
The delay line is segmented into a first group of delay units (sampling window) and a second group of delay units (tracking section). The sampling window contains N delay units for N-bit resolution, while the tracking section contains additional delay units that can be selectively bypassed. This segmentation allows the system to maintain high resolution capability when needed while reducing active components for lower resolution operations.
Solution Approach 2:
The patent implements dynamic bypassing of delay units in the tracking section through control logic that adjusts the number of active delay units based on the current measurement range. The bypassing mechanism allows the delay line to dynamically adapt its effective length, reducing the number of active sampling latches and delay units when full resolution is not required, thereby reducing complexity and power consumption.
2Measurement precision
If the number of detection units and sampling latches is increased to achieve high bit resolution, then measurement precision is improved, but footprint increases
Solution Approach 1:
The delay line is divided into a sampling window portion and a tracking section portion. The sampling window contains the essential N delay units required for N-bit resolution, while the tracking section contains additional delay units that can be selectively bypassed. This segmentation allows the system to maintain high resolution capability when needed while reducing active components for lower resolution operations.
Solution Approach 2:
The patent implements dynamic bypassing of delay units in the tracking section through control logic that adjusts the number of active delay units based on the current measurement range. The bypassing mechanism allows the delay line to dynamically adapt its effective length, reducing the number of active sampling latches and delay units when full resolution is not required, thereby reducing complexity and power consumption.
3Measurement precision
If the number of detection units and sampling latches is increased to achieve high bit resolution, then measurement precision is improved, but current consumption increases
Solution Approach 1:
The patent implements dynamic bypassing of delay units in the tracking section through control logic that adjusts the number of active delay units based on the current measurement range. The bypassing mechanism allows the delay line to dynamically adapt its effective length, reducing the number of active sampling latches and delay units when full resolution is not required, thereby reducing complexity and power consumption.
Solution Approach 2:
The system changes the operational parameters of the delay line by dynamically adjusting the number of active delay units and sampling latches based on the required measurement precision. When lower resolution is sufficient, fewer components are activated, reducing current consumption. The control logic monitors the input signal characteristics and adapts the delay line configuration accordingly.
Data Source
AI summary
This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units.