Window-Discriminator Signal Conversion for High-Bandwidth Analog Inputs
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in converting high-bandwidth analog signals with high signal-to-noise ratio and resolution, leading to energy consumption and latency issues, especially in applications like medical detectors and biology research, where signal processing close to the sensor is impractical.
Innovation Solution
A method involving a first converter unit with window discriminators dividing the signal range into sub-ranges, outputting binary signals, followed by optional additional converter units for enhanced resolution, using digital-to-analog conversion and amplification to form differential signals, enabling high-speed analog signal processing without full digitization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high sampling rate and high resolution ADC is used to convert high-bandwidth analog signals, then signal-to-noise ratio and signal fidelity are improved, but energy consumption and device complexity increase significantly
Solution Approach 1:
The patent divides the analog signal conversion process into multiple stages using a tree-structured converter system. Instead of using a single high-resolution ADC, the system segments the conversion into multiple lower-resolution conversion stages, where each stage processes a portion of the signal. This segmentation reduces the instantaneous complexity and energy consumption of each converter while maintaining overall high signal-to-noise ratio through the multi-stage approach.
2Measurement precision
If a high sampling rate ADC is used to preserve signal energy, then signal fidelity is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent employs a tree-structured converter system that segments the high-fidelity conversion task into multiple smaller conversion stages. Each stage uses a simpler converter with fewer resources, but the combined output of multiple stages achieves the same or better signal fidelity as a single high-resolution ADC. This segmentation approach significantly reduces device complexity and space requirements.
Solution Approach 2:
The patent transitions from a single-dimension high-resolution conversion approach to a multi-dimensional tree-structured approach. Instead of increasing resolution in one dimension (single ADC with high bits), the system distributes conversion across multiple dimensions (multiple converters in a tree structure), achieving high signal fidelity through spatial distribution rather than concentrating complexity in a single device.
3Productivity
If digital signal processing is performed close to the sensor, then processing speed is improved, but energy consumption increases due to high-bandwidth digital data transmission
Solution Approach 1:
The patent applies partial digitization rather than complete digitization. The tree-structured converter system performs partial conversion of the analog signal, producing intermediate digital representations that are sufficient for certain processing tasks without requiring full high-resolution digital conversion. This partial action approach enables processing close to the sensor with reduced energy consumption compared to full digitization, while still achieving improved processing speed.
Data Source
Figure 1
Figure 2~3
AI summary
In the method for converting a constant or variable electrical analog signal whose magnitude lies between a minimum value and a maximum value, a first converter unit (10) is provided which has an input (12) and a plurality of outputs (18.1 to 18.8) and a plurality of window discriminators (16.1 to 16.8). The value range between the minimum value (MIN) and the maximum value (MAX) is divided into individual, adjacent sub-ranges. Each window discriminator (16.1 to 16.8) is assigned a different one of the sub-ranges. The analog signal (14) is fed to the input (12) of the first converter unit (10), whereupon the window discriminator (16.1 to 16.8) to which the sub-range within which the magnitude of the analog signal (14) lies is assigned responds. This window discriminator (16.1 to 16.8) outputs at its output (18.1 to 18.8) output the output signal representing the first event, while all other window discriminators (16.1 to 16.8) output the output signal representing the second event at their outputs (18.1 to 18.8), whereby the output signals of all window discriminators (16.1 to 16.8) combined result in a digital signal with a number of bits equal to the number of window discriminators (16.1 to 16.8).