Microelectronic Die Stacks With Interior Window Wirebonding
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Solution Overview
Problem
Current microelectronic die stacking methods face challenges in reducing signal transmission lengths, minimizing costs, and improving reliability, particularly due to signal degradation and reliability issues associated with through-silicon vias and limited flexibility in wirebond pad positioning.
Innovation Solution
The introduction of microelectronic packages with a first microelectronic die having an opening or 'window' through which bond wires extend to connect with a second microelectronic die or substrate, allowing for flexible positioning and reduced signal transmission lengths, thereby enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If through-silicon vias are used to connect stacked NAND memory dice, then signal transmission length is reduced, but manufacturing cost increases and reliability deteriorates due to copper processing temperature, volume expansion during annealing, and ion migration
Solution Approach 1:
The patent extracts the problematic through-silicon via structure and replaces it with a window opening structure. The window opening eliminates copper processing, annealing, and ion migration issues while maintaining short signal transmission paths. The bond wire extends through the window opening to create electrical connections without requiring through-silicon vias, thus resolving the reliability issues associated with the conventional approach.
Solution Approach 2:
The patent uses a simpler, less expensive window opening structure instead of complex through-silicon via fabrication. The window opening can be formed through standard semiconductor processing steps without requiring expensive copper deposition and annealing equipment. This approach trades the permanent, complex via structure for a simpler opening that achieves the same electrical connection function with lower cost and improved reliability.
2Length of moving object
If through-silicon vias are used to connect stacked NAND memory dice, then signal transmission length is reduced, but manufacturing complexity increases due to increased number of expensive wafer level processing steps
Solution Approach 1:
The patent removes the complex through-silicon via fabrication steps from the manufacturing process. Instead of depositing copper, performing annealing, and managing volume expansion, the invention uses a window opening that can be formed with simpler processing. This extraction of the problematic manufacturing steps significantly reduces device complexity while maintaining the benefit of short signal transmission paths.
3Adaptability or versatility
If wirebond pads are positioned at edges of NAND memory dice for stacking, then flexibility in positioning is improved, but signal transmission length increases to the entire length of the die resulting in signal degradation due to impedance
Solution Approach 1:
The patent transitions the connection approach from surface-level wirebonding at die edges to through-die window openings. This dimensional change allows bond wires to pass through the interior of the die stack rather than traveling along the surface edges. The window openings are positioned strategically within the die to minimize signal transmission length while maintaining the flexibility to accommodate different stacking configurations and pad locations.
4Productivity
If stacking density is increased to achieve smaller and thinner packages, then productivity is improved, but signal transmission length and reliability issues worsen
Solution Approach 1:
The patent implements a nested structure where window openings are embedded within the stacked die configuration. Multiple window openings can be positioned at different locations and orientations within the die stack to accommodate various bonding schemes. This nested approach allows high integration density while maintaining short, reliable signal paths through the interior window openings rather than along the exterior surfaces.
Data Source
AI summary
A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or “window” formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or “window” in the first microelectronic die.