Windowed FEC Decoding Circuit for Low-Latency Braided Codes
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Solution Overview
Problem
Current forward error correction (FEC) methods face inefficiencies in decoding braided FEC codes, particularly in high bit rate communications, due to high latency and resource requirements, as they often require repeated decoding iterations to correct errors effectively.
Innovation Solution
The proposed solution involves a circuit and method for FEC decoding that uses a windowed approach, where multiple rows and columns of symbols are grouped and decoded in parallel, alternating between row and column decoding iterations, and includes the addition of zero padding bits to adjust the coding rate, facilitating efficient interleaving and de-interleaving of data symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated decoding iterations are performed to correct errors effectively, then error correction capability is improved, but latency increases
Solution Approach 1:
The patent divides the decoding process into multiple independent parallel decoding paths, each handling a portion of the codeword. Multiple decoders operate simultaneously on different segments of the received signal, allowing error correction to proceed in parallel rather than through sequential iterations, thereby reducing latency while maintaining correction capability.
Solution Approach 2:
The patent transitions from a single-dimensional sequential decoding approach to a multi-dimensional parallel architecture. By organizing decoders and syndromes in a two-dimensional array structure with multiple decoding paths operating concurrently, the system achieves error correction without the time penalty of repeated sequential iterations.
2Reliability
If multiple decoding iterations are performed, then error correction effectiveness is improved, but resource requirements increase
Solution Approach 1:
The patent segments the overall decoding task into multiple parallel decoding paths, each with its own syndrome calculator and decoder. This segmentation allows the system to distribute computational resources across multiple independent units rather than requiring one complex iterative decoder, reducing peak resource requirements while maintaining effectiveness.
Solution Approach 2:
The patent combines multiple parallel decoding paths into a unified error correction system. By merging the outputs of multiple decoders that operate simultaneously on different segments, the system achieves effective error correction without requiring the excessive resources that would be needed for a single comprehensive iterative decoder.
3Productivity
If parallel processing of multiple windows is implemented, then decoding efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the received signal into multiple windows or segments that can be processed in parallel. Each window has dedicated syndrome calculation and decoding resources, enabling simultaneous processing across multiple segments. This segmentation increases decoding throughput while keeping individual processing units relatively simple.
Solution Approach 2:
The patent employs a universal decoding architecture where identical decoder circuits can handle multiple different windows or segments. This multi-functionality allows the same hardware design to be reused across parallel processing paths, increasing efficiency without proportionally increasing device complexity through duplication of diverse components.
Data Source
AI summary
In one embodiment, a circuit for FEC decoding includes first and second syndrome calculation circuits, configured to calculate FEC syndromes for rows and columns of symbols in a de-interleaved format, respectively. A decoding circuit is configured to arrange the symbols into windows. Each window includes a plurality of sequential rows and sequential columns of the symbols in the de-interleaved format. The decoding circuit is configured to place N of the windows in a group and perform M decoding iterations of the windows in the group. In each decoding iteration, the decoding circuit performs FEC decoding of rows of each of the windows in the group followed by FEC decoding of columns of each of the windows in the group.