Winograd Matrix Multiplication Layout for Smaller, Faster Hardware
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Solution Overview
Problem
Existing matrix multiplication hardware designs based on the Winograd algorithm lack improvements in hardware footprint, operation speed, and double-precision support.
Innovation Solution
A matrix multiplication device utilizing a systolic array with detached core units arranged in a one-dimensional configuration, incorporating second and third accumulated value calculation units, and element value calculation units, along with input division, addition, and multiplication units to optimize matrix multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional Winograd algorithm-based matrix multiplication hardware design is used, then matrix multiplication can be performed, but the hardware footprint is large and operation speed is limited
Solution Approach 1:
The matrix multiplication device is divided into multiple independent core units (first core unit, second core unit, third core unit, fourth core unit) that can operate in parallel. Each core unit processes specific elements of the matrices independently, allowing simultaneous computation across multiple data elements and reducing the overall hardware footprint while maintaining high operation speed through parallel processing.
Solution Approach 2:
The patent transitions from a traditional two-dimensional matrix multiplication approach to a one-dimensional systolic array configuration where core units are arranged linearly. This dimensional change enables more efficient data flow and computation scheduling, reducing hardware requirements while improving operational throughput.
2Adaptability or versatility
If basic Winograd algorithm hardware design is used, then matrix multiplication is achieved, but double-precision support is lacking
Solution Approach 1:
Each core unit is designed with universal functionality to handle multiple precision types (single-precision and double-precision) through configurable data processing units. The core units can adaptively process different data precisions without requiring separate dedicated hardware paths, thereby supporting double-precision operations while avoiding a linear increase in hardware complexity.
Solution Approach 2:
The hardware design incorporates configurable parameters that allow dynamic adjustment of data precision handling. By changing operational parameters such as data width and accumulation precision, the same hardware architecture can support both single-precision and double-precision matrix multiplication, enhancing versatility without proportionally increasing device complexity.
Data Source
AI summary
A Winograd algorithm multiplies a first matrix by a second matrix to generate a third matrix. A plurality of second accumulated value calculation units, accumulates second multiplication values obtained by multiplying each of paired element values of the second matrix, a second accumulated value output unit outputting selecting and outputting one of output values of adjacent second accumulated value calculation unit and an accumulated second multiplication value as a second accumulated value, a third accumulated value output unit including a plurality of third accumulated value calculation units and generating third accumulated value, and one or more row element value calculation units, of which one row element value calculation unit accumulates first matrix element multiplication values obtained by multiplying each of the paired element values of the first matrix, and calculates element values of the third matrix using the accumulated first matrix element multiplication value and the second accumulated value.