Wire Assignment Reducing Critical Path Delay in Hardware Emulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in verifying Very Large Scale Integrated (VLSI) circuits lies in efficiently assigning wires to sockets in hardware emulation systems, particularly due to constraints in physical connections and the need to improve emulator speed, which is hindered by the limited number of sockets and the complexity of time division multiplexing.
Innovation Solution
A method that involves calculating latencies for each wire, sorting them based on latency, and iteratively assigning wires to sockets to minimize critical path delay, leaving more sockets available for critical paths, thereby improving emulator speed and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If time division multiplexing is used to assign multiple wires to limited sockets, then the number of sockets is constrained by hardware, but emulator speed deteriorates due to multiplexing overhead
Solution Approach 1:
The patent performs preliminary timing analysis to identify critical paths before wire assignment. By pre-calculating which wires belong to critical paths and assigning them priority access to sockets, the system avoids the speed penalty of multiplexing for time-sensitive signals while still utilizing TDM for non-critical wires.
Solution Approach 2:
The patent applies different assignment strategies to different wires based on their timing characteristics. Critical path wires receive dedicated or high-priority socket assignments with guaranteed timing, while non-critical wires can share sockets through TDM. This localized differentiation resolves the contradiction by optimizing for speed where needed while maintaining socket efficiency elsewhere.
2Ease of manufacture
If wires are assigned to sockets without considering latency, then assignment is simple, but critical path delay increases reducing emulator performance
Solution Approach 1:
The system performs preliminary timing analysis and identifies critical paths before conducting wire assignment. This pre-computation of timing constraints allows the assignment algorithm to prioritize low-latency paths for critical wires, ensuring optimal performance without requiring complex real-time adjustments during operation.
Solution Approach 2:
The patent changes the assignment parameters from simple socket availability to a multi-dimensional optimization that includes latency, critical path membership, and timing constraints. By modifying the assignment criteria to incorporate timing parameters, the system achieves both low complexity and low delay through a unified optimization framework.
3Productivity
If more wires are assigned to fewer sockets to maximize utilization, then socket utilization improves, but the number of available sockets for critical paths decreases
Solution Approach 1:
The patent implements differentiated socket allocation where critical path wires receive guaranteed access to a reserved subset of sockets, while non-critical wires utilize the remaining sockets through TDM. This local quality differentiation ensures that critical paths always have sufficient socket resources available while maximizing overall utilization through efficient sharing of non-critical resources.
Solution Approach 2:
The system pre-allocates a portion of sockets to critical path wires before assigning non-critical wires to remaining sockets. This preliminary reservation ensures that critical paths have dedicated resources available, while the remaining sockets can be fully utilized by non-critical wires through multiplexing, thus resolving the resource allocation contradiction.
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.