Microelectronic Wire Bonding with Compliant Layer for CTE Mismatch
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Solution Overview
Problem
Microelectronic devices face reliability issues due to mismatches in coefficients of thermal expansion (CTE) between semiconductor chips and substrates, leading to stress and disconnection in solder masses, which disrupt signal transmission, especially in fine pitch arrays used in modern microelectronic packages.
Innovation Solution
A microelectronic structure featuring wire bonds with a compliant material layer that separates and supports the wire bonds, allowing for flexibility to accommodate thermal expansion differences, and conductive metal masses that join the wire bonds to external features, ensuring robust and reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder masses are used to connect semiconductor chip to substrate, then electrical connection is achieved, but stress and disconnection occur due to CTE mismatch during thermal cycling
Solution Approach 1:
A compliant layer is introduced as an intermediary between the semiconductor chip and substrate. This layer has intermediate CTE properties between the chip and substrate, acting as a stress-absorbing mediator that reduces the impact of CTE mismatch on the solder masses during thermal cycling
Solution Approach 2:
The compliant layer changes the mechanical parameters of the assembly by providing a region with different stiffness and CTE characteristics. This parameter change allows the system to accommodate thermal expansion differences without transmitting excessive stress to the solder connections
2Area of stationary object
If chip scale packages are used to reduce assembly size, then area is reduced, but stress concentration increases due to shorter interconnections
Solution Approach 1:
The compliant layer is strategically positioned in specific regions where stress concentration is most likely to occur during thermal cycling. This local quality approach provides stress relief precisely where needed in the chip scale package structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of microelectronic connections by compensating for CTE mismatches, reducing stress and maintaining signal integrity through flexible wire bonds and robust bonding with conductive metal masses, thus improving the overall performance and longevity of microelectronic assemblies.
Implementation Method 1
A compliant material layer overlies and extends from the first surface of the semiconductor die
Implementation Method 2
wire bonds having bases joined to respective ones of the conductive elements
Implementation Method 3
conductive metal masses that join the wire bonds to external features
Data Source
AI summary
A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.