Wire-Bond Cooling Channels for High-Power Semiconductor Dies

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Solution Overview

Problem

High-power integrated circuits generate excessive heat, necessitating effective die cooling methods beyond traditional cold plates, heat sinks, and thermal interface materials to maintain semiconductor lifespan and prevent malfunction.

Innovation Solution

A system utilizing metal wires bonded to a metallized layer on a semiconductor die, forming a channel with a cover to direct cooling materials through, enhancing heat dissipation by increasing surface area contact with cooling materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If traditional cold plates, heat sinks, and thermal interface materials are used for die cooling, then cooling function is provided, but device complexity and additional component requirements increase

Engineering Contradiction:
Improvedie temperatureVSAvoidcooling system structure
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent merges the cooling channel structure directly into the semiconductor die by bonding metal wires to the metallized layer and forming channels within the die substrate itself. This integration eliminates the need for separate cold plates, heat sinks, and thermal interface materials, as the cooling function is now inherent to the die structure. The metal wires serve dual purposes as both electrical connections and cooling channel boundaries.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal wires bonded to the metallized layer serve multiple functions simultaneously: they provide electrical connectivity to the semiconductor circuitry and define the boundaries of cooling channels. This multi-functionality reduces the number of separate components needed, as the same structural elements perform both electrical and thermal management roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If cooling channels are integrated into the semiconductor die using wire bonding, then device complexity is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecooling system structureVSAvoidwire bonding precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies different wire bonding characteristics to different regions of the die based on local heat generation patterns. Wire density, wire height, wire diameter, and wire material can be varied across different areas of the metallized layer to match the thermal profile of the semiconductor circuitry. This localized optimization allows precise thermal management without requiring uniform high-precision bonding across the entire die.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention allows variation of multiple wire bonding parameters including wire density, wire height, wire diameter, and wire material composition across different regions of the die. These parameter changes enable the cooling channel geometry to be optimized for local thermal conditions while maintaining manufacturability through standard wire bonding process capabilities.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system effectively stabilizes chip package temperature without requiring cold plates, heat sinks, or thermal interface materials, improving cooling efficiency and heat dissipation.

Implementation Method 1

The plurality of metal wires arranged in a sequence such that a channel is formed by a space between the metalized layer of the semiconductor die and the upper portion of each of the metal wires that extends at least partially in parallel to the metalized layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20260011619A1Integrated Circuit Cooling Utilizing Wire Bonding On Metallized Layer
Publication Date: 2026.01.08 GOOGLE LLC
  • US20260011619A1 patent drawing
  • US20260011619A1 patent drawing
  • US20260011619A1 patent drawing

AI summary

A semiconductor die includes a metalized layer on an upper surface of the semiconductor die and a plurality of metal wires having a defined shape. At least one end of each of the plurality of metal wires is bonded to the metalized layer and an upper portion of each of the plurality of metal wires may extend at least partially in parallel to the metalized layer of the semiconductor die. The plurality of metal wires are arranged in a sequence such that a channel is formed by a space between the metalized layer of the semiconductor die and the upper portion of each of the metal wires that may extend at least partially in parallel to the metalized layer. The upper portion of each of the plurality of metal wires is configured to be flush with an inner surface of a cover. A cooling system including such a semiconductor die is also provided.