Wire Bond Free Wafer Level LED Bottom Electrodes
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Solution Overview
Problem
Conventional semiconductor devices, such as LEDs, require wire bonding for electrical connections, limiting the ability to apply packaging elements like phosphor layers or encapsulants until after device singulation and mounting, which restricts design flexibility and increases production costs.
Innovation Solution
The development of semiconductor devices with two bottom-side electrical contacts allows for wire bond-free fabrication, enabling the addition of packaging elements like phosphor layers and encapsulants at the wafer level, providing mechanical support and facilitating efficient light extraction through surface texturing and reflective layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for electrical connections, then device reliability is improved, but device complexity and production cost increase
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the LED fabrication sequence. By integrating electrical contacts directly into the semiconductor substrate during wafer-level fabrication, the invention removes the separate wire bonding step, thereby reducing device complexity while maintaining electrical connection reliability through direct metallurgical bonds.
Solution Approach 2:
The patent merges the electrical connection function with the substrate structure itself. The contact pads and conductive pathways are integrated into the semiconductor substrate during wafer fabrication, combining what were previously separate components (substrate and wire bonds) into a unified structure, thereby reducing overall device complexity.
2Reliability
If wire bonding is required, then electrical connection stability is improved, but manufacturing efficiency deteriorates
Solution Approach 1:
The patent performs preliminary action by fabricating the electrical contacts and conductive pathways directly into the semiconductor substrate during wafer-level processing, before device singulation and packaging. This preliminary integration eliminates the need for subsequent wire bonding operations, thereby improving manufacturing efficiency while maintaining connection stability through direct metallurgical bonds.
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a metallurgical integration approach. Instead of mechanically attaching wire bonds to contact pads after device fabrication, the electrical connections are created through integrated metallurgical layers formed during wafer processing, substituting a complex mechanical assembly process with a more efficient materials science-based approach.
3Reliability
If packaging elements are added after device singulation, then device performance is improved, but design flexibility deteriorates
Solution Approach 1:
The patent performs preliminary action by applying packaging elements such as phosphor layers and encapsulants at the wafer-level before device singulation. This early application allows for optimized design flexibility, as packaging features can be precisely positioned and integrated with the semiconductor structure before cutting, enabling better light extraction and optical performance while maintaining adaptability for different device configurations.
Solution Approach 2:
The patent merges the packaging process with the semiconductor fabrication process. By applying phosphor layers, encapsulants, and other packaging elements during wafer-level processing rather than as separate post-fabrication steps, the invention combines what were previously sequential operations into an integrated manufacturing flow, thereby improving both device performance and design flexibility.
4Ease of manufacture
If conventional LED fabrication is used, then manufacturing simplicity is improved, but light extraction efficiency deteriorates
Solution Approach 1:
The patent applies local quality by implementing surface texturing and optical features at specific locations on the semiconductor substrate. Rather than requiring complex manufacturing throughout the entire device structure, the invention introduces localized surface modifications and optical elements that enhance light extraction efficiency at critical interfaces, thereby improving optical performance without significantly complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables wafer-level packaging of high-efficiency LEDs, reducing production costs and allowing for flexible design specifications, while improving light extraction efficiency by eliminating wire bonds and enabling the application of light manipulation features before device assembly.
Implementation Method 1
the external quantum efficiency is limited by total internal reflection (TIR) of light from the LED's emission region that passes through the substrate
Implementation Method 2
TIR can be caused by the difference in the refractive index between the LED semiconductor and surrounding ambient, as predicted by Snell's Law
Implementation Method 3
a reflective material may be used to coat one or more of the layers of the device to enhance light extraction by reflecting light emitted from the active layers away from the substrate
Data Source
AI summary
A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.