Wire-Bond-Free Power Converter Circuit for Faster Switching
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Solution Overview
Problem
In power electronics, the use of bonding wires limits the maximum achievable current density and switching speed of semiconductor components due to parasitic inductances, restricting the performance of switching elements.
Innovation Solution
An electronic circuit design that eliminates bonding wires by directly connecting power-electronics semiconductor components to circuit carriers using chip bonding, forming integral electrical connections between multiple circuit carriers, which enhances current density and switching speed while improving thermal dissipation and mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to contact semiconductor components, then the components can be connected to circuit carriers, but parasitic inductances occur which limit current density and switching speed
Solution Approach 1:
The patent removes bonding wires from the circuit configuration entirely. Instead of using wire bonds to connect semiconductor components to circuit carriers, the invention directly integrates the semiconductor components onto the circuit carriers through chip bonding technology, thereby eliminating the source of parasitic inductances that limit switching speed and current density
Solution Approach 2:
The patent merges the semiconductor components directly with the circuit carriers by bonding the components to the circuit carrier substrate. This integration eliminates the need for separate bonding wire connections and reduces the overall inductance of the circuit by combining the component and carrier into a unified structure
2Quantity of substance
If bonding wires are used to contact semiconductor components, then electrical connections can be established, but the maximum permitted current density through the semiconductor components is limited
Solution Approach 1:
The patent extracts and removes the bonding wire connection layer from the circuit architecture. By directly bonding semiconductor chips to the circuit carrier, the design eliminates the current density limitations imposed by thin bonding wires and allows higher current densities to flow through the semiconductor components
Solution Approach 2:
The patent transitions from a three-dimensional wire bonding approach to a planar chip bonding approach. By laying the semiconductor chip flat against the circuit carrier in a two-dimensional configuration, the design enables broader current distribution paths and higher current density without the geometric constraints of wire bonds
3Reliability
If separate contacting elements are used to connect circuit carriers, then electrical connections can be made, but the device complexity and parasitic inductances increase
Solution Approach 1:
The patent combines the circuit carrier connection function directly into the semiconductor chip structure. The chip bonding process simultaneously establishes both the semiconductor-to-carrier connection and the inter-carrier connections, eliminating the need for separate contacting elements and reducing overall device complexity
Solution Approach 2:
The semiconductor chip serves multiple functions simultaneously: it acts as the active electronic component, provides its own electrical connections to the circuit carrier through direct bonding, and enables inter-carrier connectivity. This multi-functionality eliminates the need for dedicated bonding wires and separate contacting elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases current-carrying capacity, reduces parasitic inductances, and enables faster switching speeds, along with improved thermal management and compact integration, by eliminating the need for bonding wires and separate contacting elements.
Implementation Method 1
The first circuit carrier has a second via which electrically connects a first connection element, arranged between the underside of the first circuit carrier and the upper side of the second circuit carrier
Implementation Method 2
The first circuit carrier has a first via which electrically connects the upper side of the first semiconductor component to a first conductor path of the first circuit carrier
Data Source
AI summary
An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.