Wire Bond Inductors for Flip Chip RF Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design of mobile RF transceivers for 5G wireless communication devices faces challenges in achieving high Q-factor inductors with reduced area occupancy on laminate or package substrates, due to the high capacitance of duplexers requiring multiple inductors that occupy significant space.
Innovation Solution
The integration of wire bond inductors with flip chip dies, utilizing through silicon vias (TSVs) and tunable inductance configurations, allows for compact inductor designs with high Q-factor and reduced area usage by forming inductors with die-to-die, die-to-package, and package-to-die interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If printed inductors are used to compensate for high capacitance of duplexers, then the desired inductance value is achieved, but the area occupied on the laminate substrate increases significantly
Solution Approach 1:
The patent combines the inductor structure with the existing flip-chip die and package substrate interconnection structure. Wire bonds that already connect the die to the package substrate are configured to form inductor loops, merging the interconnection function with the inductance function. This eliminates the need for separate printed inductors on the laminate substrate.
Solution Approach 2:
The patent transitions from planar printed inductors on the laminate surface to three-dimensional wire bond loops that extend vertically between the die and package substrate. By utilizing the vertical dimension and the space between layers, the inductor occupies minimal lateral area on the substrate while maintaining the required inductance value.
2Reliability
If printed inductors are used for RF matching and filtering, then the required passive device functionality is provided, but the quality factor (Q-factor) decreases due to higher insertion loss
Solution Approach 1:
The patent uses wire bonds to create inductor loops that replicate the functionality of traditional printed inductors. The wire bond loops are configured to provide the same RF matching, filtering, and impedance transformation functions, but with superior electrical characteristics due to the discrete wire construction and optimized geometry.
Solution Approach 2:
The patent optimizes the wire bond loop parameters including loop area, wire diameter, and configuration to achieve high Q-factor. By carefully controlling the inductance value and minimizing parasitic effects through parameter optimization, the wire bond inductors achieve lower insertion loss compared to printed inductors.
3Reliability
If multiple inductors are placed on the laminate substrate to compensate for high capacitance, then the desired impedance transformation is achieved, but the device complexity and area occupancy increase
Solution Approach 1:
The wire bond interconnection structure serves multiple functions simultaneously: it provides electrical connection between die and package substrate, and forms inductor loops for RF matching and impedance transformation. This multi-functionality reduces the need for separate passive components and simplifies the overall device architecture.
Solution Approach 2:
The patent divides the wire bond interconnection into multiple segments or loops, where each wire bond or combination of wire bonds forms an inductor element. This segmentation allows flexible configuration to achieve the required total inductance value while distributing the structure across available space, reducing local area occupancy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces insertion loss and improves the quality factor (Q-factor) of inductors while minimizing the area occupied, supporting multiple frequency bands and enhancing the performance of RF modules in 5G devices.
Implementation Method 1
a large area or volume is specified to generate a magnetic wave or flux, which generates the inductance value
Data Source
AI summary
An integrated circuit (IC) package comprising a first die, including an active layer opposite a backside surface of the first die supporting a plurality of backside pads is provided. The IC package also incorporates a package substrate coupled to the active layer. The package pads on the package substrate correspond to the plurality of backside pads. A passive device comprising a plurality of wire bonds is coupled to the plurality of backside pads and the plurality of package pads. The passive device may also comprise a plurality of wire bonds coupled to the package pads by through silicon vias (TSVs). Multiple dies may be coupled with die-to-die wire bonds coupled to backside pads on each die.