Wire Bond Wires Replace Redistribution Layer in Wafer Packaging
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Solution Overview
Problem
The formation of a redistribution layer (RDL) in microelectronic assemblies is costly due to its complex processes involving masking, etching, and deposition, making it desirable to find a less expensive method for interconnecting microelectronic dies in wafer-level packaging.
Innovation Solution
The use of wire bond wires, where proximal ends are coupled to the microelectronic die surfaces and the distal ends extend outside the die perimeter into a fan-out region, with a molding material covering the die and wire bond wires, eliminating the need for a conventional RDL for wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redistribution layer (RDL) is used for interconnecting microelectronic dies, then electrical connections and functionality are achieved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent replaces the expensive, multi-step RDL manufacturing process with wire bond wires that are simpler, more cost-effective, and sufficient for the intended application. The wire bonds serve as disposable interconnect elements that achieve the electrical connection function without requiring complex deposition and etching operations.
Solution Approach 2:
The invention extracts and eliminates the RDL layer from the packaging structure, retaining only the essential wire bond interconnects. This removal of the redundant RDL component simplifies the overall device structure and manufacturing process while maintaining the necessary electrical connectivity between dies.
2Reliability
If a redistribution layer (RDL) is used for interconnecting microelectronic dies, then electrical connections and functionality are achieved, but manufacturing cost increases
Solution Approach 1:
The patent employs wire bond wires as a cost-effective alternative to expensive RDL manufacturing. The wire bonds are simpler, more economical components that achieve the same electrical interconnection function without requiring costly deposition, etching, and masking processes associated with RDL fabrication.
3Device complexity
If wire bond wires are used instead of RDL, then manufacturing cost and complexity are reduced, but additional thickness is added to the reconstituted wafer
Solution Approach 1:
The patent transitions from planar RDL interconnects to three-dimensional wire bond structures. The wire bonds extend vertically and laterally from the die surfaces, utilizing the third dimension (height) to achieve interconnections that would otherwise require multiple stacked RDL layers, thereby reducing overall wafer thickness despite the added vertical dimension of individual bonds.
4Adaptability or versatility
If wire bond wires extend outside die perimeter into fan-out region, then interconnect flexibility and routing options are improved, but device footprint and packaging complexity increase
Solution Approach 1:
The patent segments the wire bond interconnect structure into distinct functional zones: vertical bonds for direct die attachment, lateral bonds extending into the fan-out region for routing flexibility, and bonds that can be trimmed or left extended based on specific application requirements. This segmentation allows optimization of both interconnect flexibility and device footprint for different packaging scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost and complexity of interconnecting microelectronic dies by using wire bond wires instead of RDLs, allowing for efficient wafer-level packaging with less added thickness to the reconstituted wafer, enabling scalable and cost-effective microelectronic package formation.
Implementation Method 1
A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die
Implementation Method 2
A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material
Data Source
AI summary
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.