Wire-Free Chip Module Using Lead Frame Conductive Patterns
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Solution Overview
Problem
Traditional System on Chip (SOC) packaging techniques for semiconductor power circuits face issues such as high manufacturing cost, power loss, large parasitic inductance, limited current capability, and a large package size, making them unsuitable for high current and high switching frequency applications.
Innovation Solution
A wire-free chip module using a conductive pattern formed from a lead frame with integrated circuit and passive components bonded to it, eliminating the need for wire bonds and PCB traces, which reduces parasitic inductance and power dissipation, and allows for high current density and switching frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonds and PCB traces are used for interconnection, then manufacturing is easier and more readily available, but parasitic inductance increases and current capability is limited
Solution Approach 1:
The patent extracts and eliminates the wire bonds and PCB traces from the interconnection system, replacing them with a wire-free chip module architecture where conductive patterns are directly formed on the substrate, thereby removing the source of parasitic inductance while maintaining manufacturing feasibility
Solution Approach 2:
The patent merges the interconnection function into the substrate itself by forming conductive patterns directly on the substrate, combining the substrate and interconnection structure into a unified component that eliminates separate wire bonds and traces, reducing parasitic inductance without complicating manufacturing
2Ease of manufacture
If wire bonds and PCB techniques are used, then component interconnection is achieved, but power loss in interconnections increases
Solution Approach 1:
The patent removes the wire bonds and PCB trace interconnections that cause power loss, replacing them with direct conductive patterns on the substrate, thereby eliminating the resistive losses associated with traditional interconnection methods while maintaining component connectivity
Solution Approach 2:
The patent combines the interconnection function with the substrate structure by forming conductive patterns directly on the substrate, eliminating separate interconnection elements and their associated power losses, achieving both connectivity and energy efficiency
3Ease of manufacture
If SOC packaging with wire bonds is used, then semiconductor power circuits can be assembled, but package size has large footprint and thermal dissipation is poor
Solution Approach 1:
The patent merges multiple functions (interconnection, support, thermal management) into the substrate structure itself, eliminating the need for separate wire bonds and reducing the overall package footprint while maintaining assembly capability through direct mounting techniques
Solution Approach 2:
The patent transitions from a three-dimensional wire bond architecture to a planar conductive pattern architecture on the substrate, reducing vertical height and lateral footprint while maintaining electrical connectivity through two-dimensional conductive traces
4Ease of manufacture
If wire bonds are used for interconnection, then component connectivity is achieved, but current capability is limited
Solution Approach 1:
The patent removes the wire bonds that limit current capability and replaces them with conductive patterns formed directly on the substrate, which can be designed with higher current carrying capacity while maintaining ease of component connectivity
Solution Approach 2:
The patent changes the physical parameters of the interconnection structure by using conductive patterns with larger cross-sectional area and optimized trace geometry on the substrate, increasing current carrying capacity while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The wire-free chip module achieves low manufacturing costs, reduced power loss, and a compact size, making it suitable for high current and high frequency semiconductor power circuits with improved thermal dissipation and interconnection efficiency.
Implementation Method 1
the integrated circuit and the passive component bonded to the plurality of pads by solder
Data Source
AI summary
A wire-free chip module and method. The wire-free chip module including a conductive pattern formed from at least a portion of a lead frame, the conductive pattern including a plurality of pads; at least two electrical components that includes an integrated circuit and a passive component, the integrated circuit and the passive component bonded to the plurality of pads by solder; and wherein the conductive pattern is disposed to interconnect at least a portion of the integrated circuit with the passive component.