Wire-Free Chip-Scale QFN Packaging for RF Heat Dissipation
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Solution Overview
Problem
Current packaging systems for high-frequency integrated circuits face challenges with thermal performance, size constraints, and reprocessing difficulties due to the use of connecting wires, which also lead to issues like bending, cracking, and parasitic effects in classical solder assembly methods.
Innovation Solution
A Chip-Scale QFN plastic packaging system that eliminates connecting wires by using a protective coating, QFN side and base connections, an on-chip protective layer, a conductive back surface layer, and direct contact connections to enhance electrical and thermal performance while being compatible with standard SMD bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connecting wires are used in packaging systems, then electrical connections can be established, but parasitic effects occur and thermal performance deteriorates
Solution Approach 1:
The patent removes connecting wires from the packaging system entirely. Instead, it uses direct contact connections where the chip's contact pads make direct electrical and thermal contact with the package substrate's contact pads, eliminating the harmful parasitic effects of wire connections while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent merges the electrical connection function and thermal conduction function into a single direct contact structure. The same contact pads that establish electrical connections also serve as thermal pathways, eliminating the need for separate wire connections and improving overall system performance.
2Object-generated harmful factors
If direct contact connections are used without connecting wires, then parasitic effects are eliminated, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and positioning structures during the package substrate manufacturing stage, before the chip is mounted. These preliminary positioning features guide the chip placement process, ensuring accurate alignment of contact pads without requiring extremely tight tolerances during assembly.
3Temperature
If chip size is increased to improve thermal contact, then thermal performance improves, but mechanical stress and cracking increase
Solution Approach 1:
The patent concentrates the thermal management function at the local level where the chip contacts the package substrate. By providing direct thermal contact through the contact pads and underlying thermal vias, efficient heat dissipation is achieved without requiring a large chip area, thus avoiding mechanical stress and cracking issues.
4Ease of manufacture
If classical solder assembly methods are used, then connections can be established, but reprocessing becomes difficult
Solution Approach 1:
The patent removes the solder layer from the connection process. By using direct contact connections between chip pads and package substrate pads, the assembly becomes reworkable and reprocessable without the need to remove and reapply solder, enabling easier repair and modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides high electrical and thermal performance, reduces packaging size, and allows for reliable reprocessing, addressing the limitations of existing systems by ensuring efficient thermal management and compatibility with standard PCB bonding processes.
Implementation Method 1
at least one conductive back surface layer (8), configured to establish electrical, and thermal connection between the semiconductor chip (5) and the QFN packaging base
Implementation Method 2
at least one QFN base connection (4), configured to be located on the base surface of the integrated circuit, to ensure the connection of at least one of the RF and/or DC connections on the PCB to the integrated circuit and to increase the thermal contact surface with the PCB
Data Source
Figure 1
AI summary
The invention relates to a Chip-Scale QFN (Chip Scale QFN, CSQFN) plastic packaging system (1) for high frequency integrated circuits with high electrical and thermal performance, that does not use connecting wires, which are inexpensive and reliable, whose connection to PCB can be reprocessed and that are compatible with standard SMD bonding processes on PCB.