Conductive Wire Interconnects for Miniaturized Chip Packages
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Solution Overview
Problem
Conventional package structures, such as POP and 3D IC chip stacking, face challenges in miniaturization due to the size limitations of solder balls and the high cost and time-consuming process of forming through silicon vias (TSVs) in silicon interposers.
Innovation Solution
A package structure featuring conductive wires with diameters less than 0.15 mm and pitches less than 0.3 mm, bonded to conductive connection portions and encapsulated with exposed ends for electrical connection to a circuit layer, eliminating the need for silicon interposers and allowing for reduced package size and increased I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If solder balls are used for electrical connection in POP structure, then electrical connection is achieved, but package size cannot be reduced due to minimum pitch requirements
Solution Approach 1:
The patent changes the connection parameter from spherical solder balls to wire-shaped conductors, fundamentally altering the geometric parameter from diameter-based spacing to length-based routing. This allows pitch reduction because wires can be routed around obstacles and don't require the same clearance margins as spherical connectors, enabling smaller package footprints while maintaining reliable electrical connections
Solution Approach 2:
The patent introduces an intermediary substrate layer with conductive patterns that mediates between the stacked packages. Instead of direct solder ball-to-solder ball connections requiring large pitch, the wire conductors act as intermediaries that can be routed through the substrate, allowing smaller spacing between connection points while maintaining electrical functionality
2Volume of moving object
If silicon interposer with TSVs is used for 3D IC stacking, then miniaturization is achieved with fine pitch connections, but fabrication cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the silicon interposer component entirely from the packaging structure. By removing this expensive intermediate substrate that requires TSV fabrication, the design achieves miniaturization through alternative means (wire conductors on simpler substrate) without incurring the high costs associated with silicon interposer processing, etching, and metal filling
Solution Approach 2:
The patent replaces the expensive, complex silicon interposer with a simpler, cheaper organic or ceramic substrate that serves the same functional purpose of providing electrical interconnection. This cheaper substrate material and structure achieves the miniaturization goal without the high fabrication costs of silicon-based solutions
3Productivity
If silicon interposer with TSVs is used for high I/O count chips, then I/O density increases, but fabrication time increases due to complex etching and filling processes
Solution Approach 1:
The patent performs preliminary routing planning of wire conductors on the substrate before final assembly, allowing for optimized I/O density without the time-consuming TSV formation steps. The conductor paths are designed and positioned in advance, enabling high I/O density to be achieved through pre-planned wire routing rather than through slow TSV etching and filling operations
Data Source
AI summary
A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.