Wire-like Link for FPGA Hardware Accelerator Latency
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Solution Overview
Problem
Simulating complex system-on-chip and multiple processor cores on a single chip is becoming expensive and challenging due to the need for cycle accuracy and reproducibility in Field Programmable Gate Array (FPGA) based hardware accelerators, which require high-speed multiplexing and demultiplexing of signals across FPGAs, introducing latency and alignment issues.
Innovation Solution
A wire-like link system using serializers and deserializers operating at different clock frequencies to minimize latency and ensure cycle accuracy and reproducibility, with techniques like bit, word, and block alignment, and metastability detection to maintain synchronization across FPGAs, allowing for efficient data transfer without additional latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signals are multiplexed and demultiplexed across FPGAs to enable simulation of complex chips, then simulation capability is improved, but latency and alignment issues are introduced
Solution Approach 1:
A wire-like link is introduced as an intermediary communication channel between FPGAs, consisting of a serializer that converts parallel signals to serial form, a transmission medium, and a deserializer that converts back to parallel signals. This intermediary structure enables efficient signal transfer while maintaining cycle accuracy by operating at a higher clock frequency than the DUT blocks.
Solution Approach 2:
The wire-like link operates at a different clock frequency parameter than the DUT blocks. Specifically, the serializer and deserializer operate at a higher frequency to ensure that the total latency (serialization time + transmission time + deserialization time) remains less than one DUT clock cycle, thereby changing the temporal parameter to eliminate latency issues.
2Productivity
If hardware accelerators are used to speed up chip simulation, then simulation speed is improved, but cycle accuracy and reproducibility become challenging to maintain
Solution Approach 1:
The wire-like link is pre-configured with a fixed latency that is guaranteed to be less than one DUT clock cycle. This preliminary design ensures that signal transmission between FPGAs does not introduce variable delays that would compromise cycle accuracy, allowing the hardware accelerator to maintain both high speed and precise timing behavior.
3Adaptability or versatility
If multiple FPGAs are interconnected to simulate system-on-chip designs, then design complexity handling is improved, but synchronization and alignment issues worsen
Solution Approach 1:
The wire-like link acts as a standardized intermediary interface between multiple FPGAs, providing a uniform method for signal transmission. This standardization simplifies synchronization by ensuring that all inter-FPGA communications follow the same protocol and timing characteristics, reducing the overall synchronization complexity despite the increased number of FPGAs.
Data Source
AI summary
First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.