Wire Misalignment Reduction in Circuit Routing
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Solution Overview
Problem
Existing electronic design automation (EDA) systems face challenges in generating circuit designs with reduced misalignment and improved slew rate performance, particularly in the routing of wires, as current methods may not adequately optimize for wire misalignment and timing constraints.
Innovation Solution
The proposed solution involves determining misalignment in wire placement during the routing process and adjusting placements to minimize misalignment, using a method that considers wire length and overlap, and iteratively reassigning wire placements to improve alignment and reduce the number of vias, thereby enhancing timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional routing methods are used to generate circuit designs, then routing can be completed with standard processes, but wire misalignment and slew rate performance are not adequately optimized
Solution Approach 1:
The system performs preliminary determination of misalignment in wire placements before finalizing the routing. By calculating misalignment values and identifying parent-child wire relationships in advance, the system can proactively adjust placements to minimize misalignment before the routing is completed, thereby improving wire alignment without adding significant complexity to the final routing process.
2Reliability
If wire placements are adjusted to minimize misalignment, then alignment and slew rate performance improve, but the number of possible placements increases
Solution Approach 1:
The system applies local quality by focusing misalignment optimization on specific critical regions where parent-child wire relationships exist. Rather than uniformly optimizing all wire placements, the system identifies specific wire segments that require alignment adjustment and applies targeted modifications to those local areas, improving slew rate performance without unnecessarily complicating the overall placement assignment process.
Solution Approach 2:
The system performs partial action by selectively adjusting only those wire placements that contribute to misalignment in parent-child relationships, rather than reassigning all wire placements. This targeted approach achieves the necessary alignment improvements for slew rate performance while avoiding the excessive complexity that would result from comprehensive reassignment of all placements.
3Manufacturing precision
If iterative reassignment of wire placements is performed to improve alignment, then misalignment reduces and timing performance improves, but computational time and processing increase
Solution Approach 1:
The system implements feedback by calculating misalignment values for wire placements, using these calculations to identify parent-child wire relationships that require adjustment, performing iterative reassignment to reduce misalignment, and then re-evaluating the alignment. This closed-loop feedback process continues until misalignment is minimized, achieving improved wire alignment and timing performance while managing computational time through targeted iterations rather than exhaustive search.
Data Source
AI summary
Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.