Wire Bonding Pad Via Layout to Prevent Conductive Film Peeling

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Solution Overview

Problem

In semiconductor devices, stress on conductive films bonded with wires often leads to peeling issues, particularly due to residual stress and uneven interfaces between conductive films and interlayer dielectric films, which can result in manufacturing defects and reduced reliability.

Innovation Solution

The semiconductor device design includes a first conductive film and a second conductive film separated by an interlayer dielectric film with a step portion, where the second conductive film has a higher thickness and is bonded with a wire, and through terminal portions that connect the films, dispersing stress and preventing peeling by creating a stopper effect with the step portion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the second conductive film is made thicker to improve stress resistance, then reliability is improved, but manufacturing complexity increases due to the need for step portions and varied thickness control

Engineering Contradiction:
Improvepeeling preventionVSAvoidfilm structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interlayer dielectric film is segmented into a first portion and a second portion with different thicknesses, creating a step portion that accommodates the thicker second conductive film. This segmentation allows the conductive film to have varied thickness without requiring the entire structure to be complex, resolving the contradiction between reliability improvement through thickness increase and manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second conductive film is made thicker only in specific regions where stress resistance is most needed, rather than uniformly throughout. The interlayer dielectric film's step portion provides localized support where required. This local quality approach improves peeling prevention in critical areas while maintaining simpler structure elsewhere, balancing reliability and manufacturing complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If via holes are arranged in portions other than right below the electrode pad to improve current distribution, then electromigration is reduced, but stress concentration occurs leading to peeling

Engineering Contradiction:
Improveelectromigration resistanceVSAvoidconductive film stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The step portion of the interlayer dielectric film acts as a counterweight or stopper that provides mechanical support to the conductive film. This counteracts the stress concentration that would otherwise occur when via holes are positioned away from the electrode pad center, allowing improved current distribution without sacrificing stress resistance and preventing peeling.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

3Reliability

If multiple vias are divided into groups surrounding the pad opening to prevent current crowding, then electromigration is reduced, but the conductive film stress increases due to distributed via locations

Engineering Contradiction:
Improvecurrent distributionVSAvoidconductive film stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The step portion of the interlayer dielectric film serves as an intermediary mechanical support structure between the conductive film and the substrate. It provides localized reinforcement at the step portion that compensates for the stress distributed across multiple via locations, allowing the via groups to be arranged for optimal current distribution while the step portion prevents stress-induced peeling.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240413107A1Semiconductor device having a wire bonding pad structure connected through vias to lower wiring
Publication Date: 2024.12.12 FUJI ELECTRIC CO LTD
  • US20240413107A1 patent drawing
  • US20240413107A1 patent drawing
  • US20240413107A1 patent drawing

AI summary

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.