Semiconductor Wire Rasterization for Neural Parasitic Modeling
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Solution Overview
Problem
Existing techniques struggle to accurately model parasitic capacitance, resistance, and inductance in semiconductor designs, especially at smaller process geometries, leading to issues with circuit delay, energy consumption, power distribution, and reliability, and require multiple iterations to achieve manufacturable designs.
Innovation Solution
A method using neural networks to rasterize wire structures into pixel-based definitions, generating curvilinear shapes, and employing field solvers to calculate parasitic parameters, leveraging GPU or TPU architectures for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional field solver methods are used to calculate parasitic parameters, then accuracy can be maintained, but computation time increases significantly
Solution Approach 1:
The patent pre-calculates and stores parasitic parameters for various wire structure configurations in lookup tables before actual design analysis. This preliminary computation allows rapid retrieval during parasitic extraction, eliminating the need for time-consuming real-time field solver execution while maintaining accuracy through pre-computed reference data
Solution Approach 2:
The patent creates simplified representations (rasterized images) of complex wire structures that capture essential geometric features. These copied representations are used instead of full geometric models in parasitic calculations, reducing computational complexity while preserving the information needed for accurate parasitic parameter extraction
2Measurement precision
If complex wire structures are analyzed in detail, then parasitic modeling accuracy improves, but computational complexity increases
Solution Approach 1:
The patent extracts only the essential geometric features of wire structures by rasterizing them into pixel-based representations. This extraction process removes unnecessary geometric details while retaining the critical spatial relationships and dimensions needed for parasitic calculations, thereby reducing computational complexity without sacrificing modeling accuracy
Solution Approach 2:
The patent transforms continuous geometric parameters into discrete pixel-based parameters through rasterization. This parameter transformation simplifies the mathematical operations required for parasitic extraction while maintaining sufficient precision for accurate modeling of complex wire structures
3Reliability
If multiple iterations are performed to achieve manufacturable designs, then design quality improves, but development time increases
Solution Approach 1:
The patent performs parasitic parameter extraction and analysis earlier in the design process using pre-computed lookup tables and simplified models. This preliminary analysis provides sufficient information for design decisions without requiring multiple full-accuracy iterations, thereby reducing development time while ensuring design manufacturability
Data Source
AI summary
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.