Wire Resistance Approximation in VLSI Layouts
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Solution Overview
Problem
Design Automation Software Applications face significant memory and performance consumption issues when calculating parasitic capacitance and resistance values due to width bias in chip designs, particularly because they must account for contextually sensitive width variations and simultaneous determination of spacing-dependent biases on both sides of wire shapes, which can lead to late calculation errors and storage challenges.
Innovation Solution
An approximate electrical performance value is determined by calculating separate full biases for each side of a target wire shape and combining them, allowing for design validation without the need for simultaneous determination of both spacing-dependent biases, thereby reducing memory and performance consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DA applications store the effects by edge rather than by wire to account for contextually sensitive width biasing, then the accuracy of resistance and capacitance calculations is improved, but the memory consumption doubles
Solution Approach 1:
The patent segments the width bias calculation into two independent parts: spacing-dependent bias (calculated once for the wire) and edge-dependent bias (calculated separately for each edge). This segmentation allows the edge-dependent effects to be averaged rather than fully stored, reducing memory consumption while maintaining calculation accuracy.
Solution Approach 2:
The patent applies partial action by calculating only the necessary portion of the bias effect. Instead of storing complete edge-by-edge bias data for all edges, it calculates the average edge-dependent bias and applies it partially to the resistance and capacitance calculations, achieving sufficient accuracy without full storage overhead.
2Ease of operation
If DA applications use a scanline to determine spacing to neighboring wire shapes, then the processing sequence is simplified, but the ability to determine complete bias simultaneously is lost
Solution Approach 1:
The patent applies preliminary action by calculating the spacing-dependent bias for each wire before processing its edges. The scanline determines spacing to neighbors, and this spacing-dependent bias is calculated and stored in advance. Then, when edge-dependent bias needs to be calculated, the spacing-dependent bias is already available, allowing complete bias determination without requiring simultaneous knowledge of both sides.
3Measurement precision
If DA applications calculate resistance and capacitance values each time a wiring layout change is made to validate design specification, then the design validation accuracy is improved, but the processing time and performance consumption increase
Solution Approach 1:
The patent segments the bias calculation into spacing-dependent and edge-dependent components. The spacing-dependent bias is calculated once per wire based on scanline results, while the edge-dependent bias is calculated separately for each edge. This segmentation allows for more efficient recalculation when layout changes occur, as only the affected edge-dependent portions need to be updated rather than performing complete recalculations.
Data Source
AI summary
The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.