Staircased Die Package With Vertical Wire Reveal for Panel Testing

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Solution Overview

Problem

The challenge in testing stacked memory packages is that probe cards with a rectangular array of probes are not well-suited for testing circular wafers, leading to inefficient and costly wafer-level testing processes.

Innovation Solution

The implementation of multiple staircased dies with vertical wire bonds or interconnect bars that protrude above a molding layer, allowing for panel-level testing and potentially eliminating the need for a redistribution layer, thereby improving throughput and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If wafer-level testing with rectangular probe cards is used for circular wafers, then testing can be performed at wafer level, but the rectangular array of probes is not well-suited for circular wafers leading to inefficient and costly processes

Engineering Contradiction:

Improvetesting efficiencyVSAvoidmanufacturing cost

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent transitions from wafer-level testing to panel-level testing by stacking multiple dies in a three-dimensional configuration. This dimensional change allows the use of rectangular probe cards on panel structures rather than circular wafers, resolving the mismatch between probe card geometry and wafer shape while improving testing efficiency and reducing costs

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If multiple memory dies are stacked vertically to increase memory capability, then memory capacity increases in smaller spaces, but the complexity of packaging and interconnection increases

Engineering Contradiction:

Improvememory capacityVSAvoidpackaging complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the packaging process into discrete stages: die stacking, wire bonding, and molding. By segmenting the complex packaging process into manageable steps with standardized interfaces, the patent reduces overall packaging complexity while enabling vertical stacking of multiple memory dies to increase capacity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal packaging structure that can accommodate multiple types of dies (memory and logic) in vertical stacks. The standardized wire bonding and molding process serves multiple functions: electrical interconnection, mechanical support, and environmental protection, thereby reducing overall system complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of operation

If vertical wire bonds protrude from the molding layer, then panel-level testing becomes enabled, but the wire bonds must extend above the top surface of the molding layer

Engineering Contradiction:

Improvetesting accessibilityVSAvoidwire bond length

Core Design Contradiction:

Ease of operationVSLength of stationary object

Solution Approach 1:

The patent performs wire bonding before the final molding step, allowing wire bonds to protrude temporarily for testing purposes. This preliminary action enables panel-level testing accessibility while the extended wire bond length is only temporary during the testing phase, after which the package is finalized

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250329673A1Direct Wire Reveal Package

Publication Date: 2025.10.23 APPLE INC

AI summary

Electronic packages and package-on-package structures are described. In an embodiment, an electronic package include multiple staircased dies and multiple vertical wire bonds encapsulated by a molding layer, where the multiple vertical wire bonds protrude from a top surface of the molding layer so that the vertical wire bonds stand proud above a top surface of the molding layer.