Wire Segment Temperature Extraction via Finite Element Sub-modeling
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Solution Overview
Problem
Current technologies face challenges in accurately predicting local temperature rises on wire segments due to Joule heating and self-heating in complex chip designs, leading to pessimistic results from foundry formulas that do not account for actual layout geometries, resulting in inaccurate thermal field simulations and potential electromigration failures.
Innovation Solution
The use of finite element methods and sub-modeling technologies to calculate and extract temperature rises on wire segments by generating thermal-aware power maps, subdividing wire geometry into segments, and combining thermal field solutions with package-level thermal profiles, allowing for precise temperature prediction and thermal stress analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If foundry formulas are used to predict wire temperature, then the calculation is simple and fast, but the results are pessimistic and inaccurate due to not accounting for actual layout geometries
Solution Approach 1:
The chip layout is divided into multiple tiles, and each tile is further subdivided into wire segments. This segmentation allows the complex thermal analysis to be broken down into manageable sub-problems that can be solved independently and then combined, improving both accuracy and computational efficiency.
Solution Approach 2:
The patent applies different thermal analysis methods to different regions of the chip based on their specific characteristics. Wire segments are classified into different types (e.g., power wires, signal wires, ground wires) and analyzed with appropriate thermal models that account for their specific geometry, material properties, and thermal environments.
2Measurement precision
If detailed finite element analysis is performed on the entire chip, then temperature prediction accuracy is improved, but computational time and resources increase significantly
Solution Approach 1:
The chip is divided into tiles, and only critical wire segments within these tiles undergo detailed finite element analysis. Other regions use simplified thermal models or results from adjacent tiles, significantly reducing the overall computational burden while maintaining accuracy where it matters most.
Solution Approach 2:
The patent employs a multi-scale modeling approach where detailed finite element models of wire segments are nested within a coarser tile-level thermal model, which in turn is nested within the overall chip-level thermal model. This hierarchical structure allows efficient computation at each level while capturing detailed local effects where necessary.
3Measurement precision
If thermal coupling among wires is considered, then temperature prediction accuracy is improved, but the complexity of thermal analysis increases
Solution Approach 1:
The patent identifies and focuses thermal coupling analysis on regions where wires are in close proximity and thermal interaction is significant. For wire segments that are spatially separated or have minimal thermal interaction, simplified independent analysis is used, reducing overall complexity while capturing critical coupling effects.
Solution Approach 2:
The patent introduces thermal resistance networks as an intermediary model between detailed finite element analysis and simplified calculations. This intermediary approach efficiently captures thermal coupling effects among multiple wires by representing heat flow paths through equivalent thermal circuits, balancing accuracy and complexity.
4Measurement precision
If self-heating from CMOS devices is included in the analysis, then temperature prediction accuracy is improved, but the complexity of the thermal model increases
Solution Approach 1:
Self-heating from CMOS devices is incorporated selectively in regions where device density and power consumption are high. In low-power or sparsely populated regions, simplified thermal models without detailed device self-heating are used, reducing model complexity while maintaining accuracy in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides accurate and efficient prediction of local temperature rises on wire segments, enhancing chip reliability by accounting for complex thermal couplings and layout geometries, reducing the risk of electromigration failures and improving thermal integrity.
Implementation Method 1
The solving can use a finite element field solver. The finite element field solver can use a heat conduction equation derived from Fourier's law and conservation of energy.
Implementation Method 2
The finite element field solver can use a heat conduction equation derived from Fourier's law and conservation of energy.
Implementation Method 3
Local wire temperature rises due to Joule-heating power from its average or root-mean-square (rms) current and thermal coupling among wires, where the local Joule-heating power is defined as I*I*Rwire
Implementation Method 4
Self-heating or local temperature rise from CMOS devices with devices in switching or idle mode
Data Source
AI summary
Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.