Wirebond-Free Chip Scale Package Perpendicular Lead Mounting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip scale packages (CSPs) face challenges in size reduction and efficiency due to the use of wirebonds, which limit miniaturization and increase package size, and they often require complex mounting configurations that do not fully utilize the die size and lead geometry for optimal integration with motherboards.
Innovation Solution
The implementation of chip scale packages that eliminate wirebonds by directly coupling leads to the die using conductive adhesives and orienting the leads perpendicularly to the motherboard, allowing for a reduced footprint and efficient integration without wirebonds, and utilizing lead frames with partially etched locations and tie bars for singulation and assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wirebonds are used in conventional CSPs, then electrical connectivity is achieved, but package size increases and miniaturization is limited
Solution Approach 1:
The patent extracts and eliminates the wirebond component from the CSP structure. By removing wirebonds and directly coupling leads to the die using conductive adhesives, the package size is reduced while maintaining electrical connectivity through the lead-die direct connection architecture.
Solution Approach 2:
The patent changes the mounting configuration from conventional planar orientation to perpendicular orientation relative to the motherboard. This dimensional change allows for reduced footprint and enables the leads to extend perpendicular to the motherboard surface, optimizing space utilization.
2Adaptability or versatility
If complex mounting configurations are used, then integration with motherboard is achieved, but die size utilization is suboptimal and lead geometry is not fully utilized
Solution Approach 1:
The patent employs perpendicular mounting configuration where leads extend perpendicular to the motherboard surface rather than in the planar plane. This dimensional change optimizes both die size utilization and lead geometry, achieving efficient integration with reduced footprint.
Solution Approach 2:
The patent changes the orientation parameter of lead mounting from conventional horizontal/planar configuration to vertical/perpendicular configuration. This parameter change fully utilizes lead geometry and optimizes the integration approach, achieving better space efficiency.
3Area of stationary object
If leads are oriented parallel to motherboard surface, then conventional mounting is achieved, but footprint is larger and thermal dissipation is less efficient
Solution Approach 1:
The patent orients leads perpendicular to the motherboard surface, changing from planar to vertical arrangement. This dimensional change simultaneously reduces footprint and enhances thermal dissipation by providing direct thermal pathways from die through leads to motherboard heat sinks.
Solution Approach 2:
The patent replaces conventional thermal dissipation mechanisms with direct thermal conduction through the perpendicular lead structure. The vertical lead orientation creates efficient thermal pathways that conduct heat directly to the motherboard, improving thermal management.
4Reliability
If wirebonds are used, then electrical connectivity is established, but failure mechanisms increase and handling complexity increases
Solution Approach 1:
The patent removes wirebonds from the CSP structure, eliminating the associated failure mechanisms and handling complexity. The direct lead-to-die coupling using conductive adhesives simplifies the structure and reduces potential failure points.
Solution Approach 2:
The patent merges the lead and die connection functions by directly coupling leads to the die surface using conductive adhesives. This integration eliminates the separate wirebond component and simplifies the overall structure, reducing handling complexity and failure mechanisms.
Data Source
AI summary
A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.