Wirebond-Free Power Semiconductor Package for Low Inductance Cooling
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Solution Overview
Problem
The packaging technology for power semiconductor devices limits heat dissipation and current handling capabilities, particularly due to stray inductance and the use of wirebonds, which restricts the performance of high-performance devices like silicon carbide power semiconductor dies.
Innovation Solution
A power semiconductor package design featuring leads with exposed heat exchanging portions on both sides of the housing and large electrical contact areas on the leads for improved heat dissipation and current handling, eliminating wirebonds to reduce stray inductance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging with wirebonds is used, then device complexity is reduced, but stray inductance increases and current handling capability deteriorates
Solution Approach 1:
The patent removes wirebonds from the packaging structure, eliminating the intermediate connection element between leads and semiconductor die. This extraction of the wirebond component directly reduces stray inductance and simplifies the current path, allowing direct solder connection between leads and die contact pads.
Solution Approach 2:
The patent merges the electrical connection function and mechanical support function into the lead structure itself. The leads are directly coupled to the semiconductor die contact pads, combining what were previously separate functions (wirebond for electrical connection, lead frame for mechanical support) into a unified direct-connection architecture.
2Temperature
If heat exchanging portions are exposed on both sides of housing, then heat dissipation is improved, but device complexity increases
Solution Approach 1:
The patent transitions from single-sided heat dissipation (heat exchanging portion exposed on bottom only) to dual-sided heat dissipation (heat exchanging portions exposed on both top and bottom). This dimensional change in thermal management architecture doubles the available heat exchange surface area, significantly improving heat dissipation capability.
3Reliability
If electrical contact portion area is increased to at least 7.5 mm2, then current handling capability is improved, but footprint area increases
Solution Approach 1:
The patent concentrates the current handling capability enhancement at specific locations (the electrical contact portions of the leads) rather than uniformly increasing the entire package footprint. By providing at least 7.5 mm2 of exposed electrical contact area on the leads where it is most needed for PCB connection, the design achieves high current capability without proportionally increasing overall package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation and current handling capabilities, reduces stray inductance, and increases the switching speed of power semiconductor packages, enabling them to conduct higher currents while maintaining reliability and adhering to compact packaging standards.
Implementation Method 1
The first lead includes a heat exchanging portion exposed on the top side of the housing... the heat dissipation of the power semiconductor package is improved
Implementation Method 2
heat exchanging portion exposed on the top side of the housing... heat exchanging portion exposed on the bottom side of the housing
Data Source
AI summary
A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm2 of the electrical contact portion of the first lead is available for contacting a printed circuit board. The second lead is in contact with a second electrical contact of the power semiconductor die. The second lead includes a heat exchanging portion on the bottom side of the housing and an electrical contact portion also on the bottom side of the housing.