Wirebond Stub Minimization in Microelectronic Packages
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Solution Overview
Problem
Conventional microelectronic packages occupy a larger area on circuit panels due to long unterminated stubs, which can lead to signal degradation and performance issues, especially in high-frequency applications, due to increased settling time, ringing, jitter, and intersymbol interference.
Innovation Solution
A microelectronic package design with terminals arranged in a configuration that reduces stub lengths by positioning first terminals in a central region and second terminals in peripheral regions, allowing for shorter electrical connections between packages mounted opposite each other on a circuit panel, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If terminals are positioned at peripheral edges of the package substrate, then the package structure is simplified and manufacturing is easier, but the stub length increases causing signal degradation
Solution Approach 1:
The patent transitions from a two-dimensional peripheral terminal arrangement to a three-dimensional configuration by placing terminals in the central region of the package substrate. This central positioning allows conductive elements to extend vertically through the substrate thickness, creating a compact stub structure that reduces signal path length while maintaining peripheral accessibility.
Solution Approach 2:
The patent applies different spatial qualities to different terminal groups: address terminals are positioned in the central region with vertical conductive paths, while data terminals can be positioned peripherally. This localized differentiation optimizes signal quality for address lines without compromising the overall package manufacturability.
2Reliability
If terminals are positioned in the central region of the package substrate, then stub length is reduced improving signal quality, but the package area occupied increases
Solution Approach 1:
The patent utilizes the vertical dimension (substrate thickness) to accommodate conductive elements that extend from the central region terminals to the opposite surface. This vertical routing allows compact horizontal footprint while maintaining electrical connectivity, effectively trading vertical space for horizontal compactness.
3Device complexity
If unterminated stubs are used for electrical connections, then the circuit panel structure is simplified, but signal degradation increases due to settling time, ringing, and jitter
Solution Approach 1:
The patent changes the critical parameter of stub length by repositioning terminals from peripheral to central locations. This parameter change reduces the electrical length of conductive elements, thereby decreasing settling time and minimizing signal integrity issues such as ringing and jitter, while maintaining the simplicity of unterminated stub architecture.
Data Source
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AI summary
A microelectronic package (100) can include a microelectronic element (130) mounted face up on a first surface (108) of a substrate (102), with one or more columns (138, 139) of contacts (132) in a first direction (142) along the microelectronic element front face. Columns (104A, 104B, 106A, 106B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction along surface (110). First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.