Wirebonded Multi-Die Stack Packaging for Shorter IC Interconnects

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Solution Overview

Problem

The challenge is to maintain a small form factor and provide shorter interconnect distances between dies in a multi-die package, while accommodating the increasing input/output density and shrinking dimensions of dies.

Innovation Solution

The solution involves an integrated circuit package configuration with a wire-bonded multi-die stack, where each die is embedded in an encapsulation layer and connected via electrical routing features and bonding wires, allowing for efficient signal routing and compact packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If dies are stacked vertically in a multi-die package, then interconnect distances between dies are reduced, but the complexity of electrical routing and bonding increases

Engineering Contradiction:
Improveinterconnect distanceVSAvoidrouting complexity
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar interconnection to three-dimensional vertical stacking, arranging multiple dies in the Z-direction rather than spreading them out in the X-Y plane. This dimensional change reduces interconnect distances while managing routing complexity through vertical vias and stacked bond pads.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested interconnection structures where lower dies are positioned beneath upper dies, with electrical connections routing through intermediate layers. The bond pads and vias are nested vertically, with each die's connection structure integrated within the overall stack architecture.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If input/output density of dies is increased, then functionality and performance improve, but the physical dimensions of dies must be precisely controlled

Engineering Contradiction:
Improveinput/output densityVSAvoiddie dimension control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent modifies geometric parameters of bond pads and interconnection structures to accommodate higher I/O density. By adjusting pad sizes, spacing, and vertical positioning, the design achieves increased I/O capacity while maintaining manufacturability within standard die dimension tolerances.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If bonding wires are routed around protruding bond pads, then electrical connections are established, but the bonding process becomes more complex and time-consuming

Engineering Contradiction:
Improveelectrical connectionVSAvoidbonding speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary positioning of bond pads and definition of wire routing paths before the actual bonding process. Bond pads are pre-configured with appropriate protrusion dimensions, and wire routes are predetermined, enabling faster execution of the bonding operation without compromising connection reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different bonding approaches to different regions: bond pads that protrude are connected with wire bonds that clear the protrusion, while non-protruding pads use direct bonding. This localized quality adjustment optimizes the bonding process for each specific pad configuration.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces interconnect distances and maintains a small form factor, enabling efficient signal transmission and supporting the increasing density and shrinking size of dies in multi-die packages.

Implementation Method 1

The second plurality of die-level interconnect structures are electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires

Methodology Applied
Scientific EffectWire bonding: Welding

Data Source

PatentUS20250167180A1Integrated circuit package having wirebonded multi-die stack
Publication Date: 2025.05.22 INTEL CORP
  • US20250167180A1 patent drawing
  • US20250167180A1 patent drawing
  • US20250167180A1 patent drawing

AI summary

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.