Wirebondless Wafer Level Package Plated Interconnects
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Solution Overview
Problem
Conventional semiconductor packaging methods using wirebonds result in increased package height, reduced density, and higher manufacturing costs due to the need for extended processing and expensive wirebonding techniques.
Innovation Solution
The development of a wirebondless wafer level package with plated bumps and interconnects, where a semiconductor die is mounted in a carrier strip or substrate with metal layers forming package bumps and interconnects between the die and substrate, eliminating the need for wirebonds and reducing package height through the use of plated metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonds are used to connect the die to the substrate, then electrical connection is achieved, but the package height is increased resulting in low-density packing
Solution Approach 1:
The patent extracts and eliminates the wirebond component from the packaging system. Instead of using wirebonds to connect the die to the substrate, the invention uses direct plated interconnects formed as integral parts of the substrate, thereby removing the height-increasing wirebond elements while maintaining electrical connection functionality
Solution Approach 2:
The patent transitions from three-dimensional wirebond connections (extending vertically above the substrate surface) to planar plated interconnects that lie substantially within the substrate plane. This dimensional change from vertical to lateral connectivity reduces package height while achieving the same electrical connection function
2Reliability
If wirebonding is used for interconnection, then electrical connection is achieved, but the manufacturing process becomes expensive and extended
Solution Approach 1:
The patent merges the interconnect formation process with the substrate manufacturing process. The plated interconnects are formed as integral parts of the substrate through plating processes that occur during substrate fabrication, eliminating the need for separate wirebonding steps and reducing overall manufacturing complexity and cost
Solution Approach 2:
The patent performs interconnect formation in advance during substrate manufacturing, before the die is mounted. The plated interconnects are pre-formed on the substrate surface, so that when the die is later attached, electrical connections are already established, eliminating the need for post-assembly wirebonding operations
3Reliability
If conventional wirebond packaging is used, then die connection is achieved, but density is reduced and cost increases
Solution Approach 1:
The patent replaces the mechanical wirebond system with an electrochemical plating system. Instead of mechanically attaching wirebonds to connect die to substrate, the invention uses electrochemical or electroless plating to deposit conductive material that forms integral plated interconnects, achieving connection through material deposition rather than mechanical assembly
Solution Approach 2:
The patent changes the fundamental parameter of connection method from mechanical (wirebond) to material-deposition-based (plated interconnect). This parameter change enables connections to be formed as thin, planar layers within the substrate, significantly reducing the vertical space required and increasing packing density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact, cost-effective, and efficient packaging solution with reduced manufacturing complexity, enabling higher-density integration and faster electrical connections, while allowing for additional device stacking and functionality.
Implementation Method 1
A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die
Implementation Method 2
A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die
Data Source
AI summary
A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.