Wired-OR Page Buffer Cache for Faster NAND Program Verification
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices require extended operation cycles due to program-verifying operations and suffer from reduced programming speed for sequential data programming, as they need to verify each memory cell individually and rely on a cache function that slows down the loading of subsequent data pages.
Innovation Solution
A nonvolatile semiconductor memory device with a page buffer comprising a main latch block, a cache latch block, and an output driver, where the cache latch block loads and stores next input data during the programming of a memory cell, allowing for parallel programming of multiple data pages and a wired-OR verifying operation to reduce verification time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional page buffer with sense latch is used to store data for programming operations, then data can be temporarily held and provided to bit lines, but the operation cycle is extended due to required program-verifying operations and charge sharing effects that may flip data
Solution Approach 1:
The page buffer is segmented into two independent latch circuits: a first latch circuit for holding data during programming operations and a second latch circuit for caching next programming data. This segmentation allows simultaneous operation of data programming and cache loading, eliminating the need for sequential operations and reducing overall operation cycle time while maintaining data integrity through dedicated latch functions
Solution Approach 2:
The second latch circuit loads next programming data in advance during the programming operation of current data. This preliminary action prepares the next data before it is needed, so that when the current programming operation completes, the next data is already ready in the second latch circuit, eliminating waiting time and reducing the overall operation cycle
2Ease of manufacture
If sequential data pages are programmed one after another using conventional page buffers, then each page must be fully processed before the next is loaded, but this reduces programming speed for sequential data
Solution Approach 1:
The patent enables continuous useful action by allowing the second latch circuit to continuously load next programming data during the programming operation. This overlapping of data loading and programming operations ensures that the system is always performing useful work - either programming current data or loading next data - without idle waiting periods, thereby increasing programming speed for sequential data while maintaining operational simplicity
Data Source
AI summary
Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory device includes an output driver enabling an internal output line to be unidirectional driven, thereby enabling a program-verifying operation using the wired-OR scheme.