Wired Under-Bump Structure for Simpler Wafer-Level Packaging
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is integrating a large number of electronic devices into a single silicon wafer while maintaining product yield and reliability, as the packaging process becomes increasingly complex and costly.
Innovation Solution
A semiconductor device with a wired under-bump structure is formed using a redistribution layer (RDL) that includes interconnect segments with wiring pad, under-bump, and trace portions, connected by bond wires and ball connectors, encapsulated by a non-conductive layer, allowing for wafer-level packaging and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of electronic devices are integrated into a single silicon wafer, then device functionality and compactness are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the wafer into multiple individual die units, each capable of independent packaging. The redistribution layer is segmented into separate interconnect segments for each die, allowing parallel processing and simplified manufacturing of individual packaged devices while maintaining high functionality through integration of multiple dies on the wafer.
Solution Approach 2:
The patent transitions from traditional two-dimensional packaging to three-dimensional wiring under bump structures. By routing interconnect segments underneath the bump structures rather than on the surface, the design adds a vertical dimension to interconnection, reducing surface complexity and enabling more compact device integration.
2Ease of manufacture
If traditional packaging processes are used, then manufacturing simplicity is maintained, but product yield and reliability deteriorate
Solution Approach 1:
The patent performs preliminary actions by forming the redistribution layer and interconnect segments on the wafer before individual die packaging. The under-bump wiring is established in advance during wafer-level processing, so that when dies are separated and packaged, the interconnection structure is already in place, simplifying subsequent packaging steps while ensuring reliable connections.
3Reliability
If complex packaging processes are implemented, then product reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple manufacturing steps into a unified wafer-level process. The redistribution layer formation, interconnect segment creation, and under-bump wiring are combined into a single integrated fabrication sequence performed on the entire wafer before die separation. This consolidation reduces the total number of process steps, lowers manufacturing costs, while maintaining high reliability through controlled wiring structures.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over an active side of a semiconductor die. A die pad of the semiconductor die is connected to an interconnect segment of the RDL by way of a bond wire. An encapsulating layer is formed over the active side of the semiconductor die such that exposed portions of the die pad and the bond wire are embedded in the encapsulating layer.