Wireless Channel Emulation Using Cluster Delay Line Models
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Solution Overview
Problem
Emerging wireless technologies, such as millimeter wave 5G cellular and sub-6 GHz 5G massive-MIMO cellular, require high computational resources for simulating and emulating wireless channels with large numbers of antennas and sub-paths, leading to increased costs and computational burdens in traditional methods.
Innovation Solution
A system and method for fast simulation and emulation of wireless cluster and tapped delay line models, utilizing a hardware processor, programmable memory, and sample filters to modify data signals based on control signals and channel information, reducing computational costs by optimizing operations such as beamforming and Doppler shift calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional emulation methods are used for wideband channels with large numbers of antennas and sub-paths, then accurate channel modeling is achieved, but computational cost becomes prohibitively high
Solution Approach 1:
The patent segments the channel model into cluster-level parameters and sub-path parameters. By separating the computation into hierarchical levels (clusters first, then sub-paths), the system reduces the computational burden while maintaining modeling accuracy. The cluster delay line structure divides the overall channel into multiple independent clusters, each processed separately.
Solution Approach 2:
The patent changes the parameter representation from individual sub-path parameters to cluster-level parameters (delay, gain, angle of arrival/departure). This parameter transformation reduces the total number of parameters that need to be processed, as multiple sub-paths are grouped into clusters sharing common parameters, thereby reducing computational complexity.
2Reliability
If conventional simulation procedures are used for emerging wireless technologies, then comprehensive channel evaluation is performed, but computational time and cost increase significantly
Solution Approach 1:
The patent performs preliminary computation of cluster-level parameters (delay, gain, angles) before processing individual sub-paths. By pre-calculating the cluster delay line characteristics and storing them in lookup tables, the system avoids redundant computations during actual channel simulation, significantly reducing computational time while maintaining evaluation comprehensiveness.
Solution Approach 2:
The patent uses lookup tables to store pre-computed cluster delay line parameters and spatial signature vectors. During simulation, instead of recalculating these parameters, the system copies them from the lookup tables, dramatically reducing computational time while preserving the accuracy of channel evaluation.
3Measurement precision
If full computational resources are allocated to channel emulation, then high precision channel modeling is achieved, but cost and resource requirements become prohibitive
Solution Approach 1:
The patent extracts and separates the computationally intensive parts of channel modeling (cluster-level parameters) from the routine processing (sub-path processing). By taking out the cluster delay line parameters and handling them independently with optimized algorithms, the system reduces the computational resources required for overall channel modeling while maintaining precision.
Solution Approach 2:
The patent creates a universal cluster delay line framework that can handle multiple sub-paths and clusters using the same set of parameters and algorithms. This multi-functional approach allows the system to model complex channels with fewer unique parameters, reducing the total computational resources needed while maintaining modeling precision.
Data Source
AI summary
An exemplary device for emulating a wireless channel(s) can be provided, which can include, for example, a first communication interface configured to receive a first data signal(s) from a transmitter unit(s), a hardware processor configured to receive the first data signal(s) from the first communication interface, and generate a second data signal(s) by modifying the first data signal(s) based on a test(s) being performed on the transmitter unit(s), and a second communication interface configured to receive the second data signal(s) from the hardware processor, and transmit the second data signal(s) to a receiver unit(s). A control interface can be included, which can be configured to receive a control signal(s) from the transmitter unit(s) or the receiver unit(s) and provide the control signal(s) to the hardware processor for determining the second data signal(s).