Wireless Clock Distribution via Frequency Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock synchronization methods, such as synchronous-Ethernet and IEEE 1588V.2, are ineffective when used over wireless links due to the lack of synchronization between locally generated clocks in transmitters and receivers, leading to inaccuracies and sensitivity to packet delay variations and network behavior.
Innovation Solution
A system that synthesizes a clock frequency by extracting a clock from a wired data connection, estimating errors, and adding them to a local clock frequency to create a modulated signal for wireless transmission, allowing receivers to reconstruct the clock for synchronizing a second wired data connection, using techniques like Direct Digital Synthesis and OFDM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous-Ethernet method is used to distribute clock frequency information through locking of the Ethernet clock, then clock frequency synchronization is improved, but phase and TOD information cannot be distributed
Solution Approach 1:
The patent segments the clock information distribution into multiple components: frequency information is distributed through Ethernet clock locking, while phase and TOD information are distributed separately through wireless communication. This segmentation allows each type of information to be transmitted through the most appropriate channel, resolving the limitation of synchronous-Ethernet that can only handle frequency synchronization.
2Loss of information
If IEEE 1588V.2 method is used to distribute any type of clock information, then comprehensive clock information distribution is improved, but sensitivity to packet delay variation, packet loss and network behavior increases
Solution Approach 1:
The patent introduces wireless communication as an intermediary medium to distribute clock information. Instead of relying solely on packet-based network protocols that are sensitive to delay and loss, the system uses wireless signal transmission to carry clock data, which provides more direct and reliable transmission paths less susceptible to network behavior variations.
3Adaptability or versatility
If locally generated clocks are used in transmitters and receivers over wireless links, then wireless communication flexibility is improved, but clock synchronicity between wired data connections deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where the transmitter and receiver continuously monitor and adjust their locally generated clocks based on synchronization signals exchanged over the wireless link. This feedback loop allows the system to maintain wireless communication flexibility while actively correcting clock drift to preserve synchronicity between wired data connections at both ends.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures clock synchronicity between wired data connections over wireless links, reducing inaccuracies and maintaining signal integrity despite temperature variations and network conditions.
Implementation Method 1
the clock error estimator estimates the clock frequency error between the clock frequency f2 and the clock frequency f1 by counting clock cycles of the clock frequency f2 and the clock frequency f1 over a period, and comparing the counts
Implementation Method 2
the clock adder adds the clock frequency error to the clock frequency f1 using Direct Digital Synthesis (DDS), resulting in a synthesized clock frequency f2
Implementation Method 3
a modulator modulates a data stream into a modulated signal using the synthesized clock frequency f2
Implementation Method 4
the transmitter up-converts the modulated signal into a wireless signal containing the synthesized clock frequency f2
Implementation Method 5
A receiver down-converts the wireless signal, into a down-converted wireless signal
Implementation Method 6
A de-modulator de-modulates the down-converted wireless signal into a received data stream thereby reconstructing the synthesized clock frequency f2 into a reconstructed synthesized clock frequency f2
Data Source
AI summary
A clock extractor extracts clock frequency f2, from a wired data connection feeding the transmitter with data clocked at the clock frequency f2. A clock error estimator estimates clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter. Clock adder adds the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2. A modulator uses the synthesized clock frequency f2, to modulate a data stream into a modulated signal.