Wireless Device Clock Control for Power Saving State Recovery
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Solution Overview
Problem
Wireless communication devices face issues with unpredictable behavior due to undefined data output when transitioning from a power saving state, particularly during read sequences, leading to potential failure in returning to the previous state effectively.
Innovation Solution
The implementation of a wireless communication device with a clock control unit that restarts the memory clock before the processor clock, ensuring the memory unit stabilizes before resuming operations, thereby preventing undefined data output and ensuring a proper return from the power saving state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the wireless communication device transitions to a power saving state by stopping the driving clock and reducing power supply, then power consumption is reduced, but undefined data may be output from the memory unit when returning from the power saving state during a read sequence
Solution Approach 1:
The patent applies preliminary action by detecting the read sequence state before transitioning to the power saving state and storing this detection result. When returning from the power saving state, this pre-stored information is used to determine whether to inhibit the read operation, preventing undefined data output without requiring complex real-time detection circuits.
Solution Approach 2:
The patent introduces a detection circuit and control unit as intermediaries between the memory unit and the processor. These intermediaries monitor the read sequence state and mediate the transition to/from power saving state, ensuring that undefined data conditions are prevented while maintaining power efficiency.
2Productivity
If the device returns to the normal power state by restoring the driving clock and power supply, then normal operation is resumed, but unpredictable behavior occurs due to undefined data from the memory unit
Solution Approach 1:
The patent implements feedback by continuously monitoring the read sequence state through a detection circuit and using this feedback information to control the transition to and from power saving state. The control unit receives feedback about the memory operation state and adjusts the power saving transition accordingly, preventing undefined data output while ensuring stable operation resumption.
Data Source
AI summary
A wireless communication device includes a processor, a memory unit capable of retaining data in a power saving state, a clock control unit configured to control when a clock is to be supplied to each pair of processor and memory, and a power control unit configured to control an amount of power to be supplied to the processor and the memory unit. In the power saving state, the clock control unit stops supplying the clock to the processor and the memory unit, and the power control unit reduces the amount of power supplied to the memory unit. When returning from the power saving state, the power control unit increases the amount of power supplied to the memory unit, and the clock control unit starts supplying the clock to the memory unit before starting to supply the clock to the processor.