Scalable Wireless Clock Circuitry for Multi-RAT Power Control
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Solution Overview
Problem
Multi-RAT wireless devices face inefficiencies in power consumption and communication due to varying bandwidth requirements across different radio access technologies, leading to increased resource usage and complexity in managing clock frequencies.
Innovation Solution
A scalable clock frequency system using parallel processing paths is implemented, allowing dynamic adjustment of clock frequencies based on accuracy needs, with static and dynamic clock frequencies supporting multiple RATs, and a method to allocate physical resource blocks efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the wireless device supports multiple RATs with different bandwidth requirements, then the device can operate across different standards (UMTS 3G, LTE 10, LTE 20), but the power consumption and resource requirements increase significantly
Solution Approach 1:
The patent implements dynamic clock frequency scaling that adjusts the operating frequency based on the currently active RAT and its specific bandwidth requirements. The system transitions from static high-frequency operation to dynamic frequency adjustment, lowering the clock frequency when operating at lower bandwidths (e.g., UMTS 3G) to reduce power consumption while maintaining full frequency capability when needed (e.g., LTE 20).
Solution Approach 2:
The system changes the clock frequency parameter dynamically based on the active RAT configuration. By monitoring which RAT is currently active and adjusting the clock frequency parameter accordingly, the system optimizes power consumption for each specific operating mode without sacrificing the ability to support multiple bandwidth requirements.
2Productivity
If LTE 20 is allocated 100 PRBs, then the device can support maximum bandwidth requirements, but when fewer PRBs are used, the resource allocation becomes inefficient and SNR decreases
Solution Approach 1:
The patent implements partial resource block allocation where the system allocates only the necessary number of PRBs required for the current transmission needs rather than always allocating the maximum 100 PRBs. This partial action approach matches resource allocation to actual requirements, avoiding the waste of allocating excessive resources when lower bandwidth is sufficient.
Solution Approach 2:
The system dynamically adjusts the number of active PRBs based on the current RAT and transmission requirements. This dynamic resource allocation allows the system to optimize the balance between bandwidth capacity and power efficiency by activating only the necessary number of resource blocks rather than maintaining all 100 PRBs active at all times.
3Reliability
If the clock frequency is operated at maximum for all RATs, then all standards can be supported at full performance, but power consumption increases unnecessarily for lower bandwidth RATs
Solution Approach 1:
The patent changes the clock frequency parameter based on the active RAT configuration. The system maintains full performance reliability by ensuring the clock frequency is sufficient for the current RAT's requirements, while avoiding unnecessary high-frequency operation for lower bandwidth standards. This parameter adaptation ensures each RAT operates at its optimal frequency without over-provisioning.
Solution Approach 2:
The system applies local quality optimization by tailoring the clock frequency to the specific requirements of each active RAT. Instead of applying a uniform high frequency across all RATs, the system adjusts the frequency locally according to each standard's bandwidth needs, ensuring adequate performance for each while minimizing overall power consumption.
Data Source
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AI summary
Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.