Wireless Clock Recovery Using Delay Circuits Instead of PLLs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In low-power wireless communication devices, the frequency synthesizer (PLL or VCO) consumes a significant portion of the overall power, leading to high power consumption and potential noise issues due to on/off cycles, which affects the stability of the clock frequency recovery.
Innovation Solution
A wireless communication device and method that recover a clock frequency without using a PLL or oscillator, employing a delay circuit and delay-locked loop (DLL) to generate a delayed signal, which is then used to produce a clock signal through a logical sum with the input signal, allowing for clock frequency recovery without continuous oscillator activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency synthesizer (PLL or VCO) is used for clock frequency recovery, then accurate clock frequency can be recovered, but power consumption increases significantly
Solution Approach 1:
The patent extracts the essential function of frequency synthesis from the complex PLL/VCO system and implements it using only a delay circuit and logical sum operation. By removing the frequency synthesizer component entirely and keeping only the minimal necessary elements (delay circuit + logic gate), the system achieves clock frequency recovery with dramatically reduced power consumption while maintaining the core functionality.
2Stability of the object's composition
If a PLL or oscillator is continuously activated for clock frequency recovery, then stable clock frequency is maintained, but noise increases due to on/off cycles
Solution Approach 1:
The patent employs periodic action by activating the delay circuit and logical sum operation only during the carrier-on interval when the input signal is present. The delay circuit processes the input signal periodically synchronized with the carrier waveform, generating the clock frequency without requiring continuous oscillator operation. This periodic activation eliminates the noise generated by continuous on/off cycling of traditional PLL/oscillator systems while maintaining clock frequency stability throughout the carrier-on period.
3Use of energy by moving object
If the delay time is adjusted to optimize clock frequency recovery, then power consumption is reduced, but the complexity of delay time control increases
Solution Approach 1:
The delay circuit is designed to automatically adjust its delay time based on the characteristics of the input signal, eliminating the need for external control mechanisms. The circuit self-calibrates by processing the carrier waveform and automatically setting the appropriate delay duration corresponding to the carrier-on interval. This self-service capability reduces power consumption while avoiding the added complexity that would result from external delay control circuits.
Data Source
AI summary
A device with wireless communication includes: an input receiver configured to receive an input signal having a carrier frequency; a delay circuit configured to generate a delayed signal by delaying the input signal; and a clock generator configured to generate a clock signal having a clock frequency based on the delayed signal and the input signal.