Wireless Clock Synchronization via Error Message Distribution
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Solution Overview
Problem
Existing clock synchronization methods, such as synchronous-Ethernet and IEEE 1588V.2, are ineffective when used over wireless links due to the inherent inaccuracies of oscillators and sensitivity to packet delay variations, packet loss, and network behavior, leading to difficulties in maintaining clock synchronicity between wired networks connected via wireless interfaces.
Innovation Solution
A system that extracts a clock frequency from a wired data connection, estimates and transmits clock errors over a wireless link, and uses a clock adder to synthesize a corrected clock frequency for the receiving wired data connection, ensuring clock synchronicity through Direct Digital Synthesis (DDS) and modulation techniques like OFDM, Single Carrier QAM, or CDMA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous-Ethernet method is used to distribute clock, then clock frequency information can be distributed through locking of the Ethernet clock, but phase and TOD information cannot be distributed
Solution Approach 1:
The patent segments clock synchronization into multiple independent components: frequency synchronization (handled by synchronous-Ethernet locking) and phase/TOD synchronization (handled by separate timestamp exchange mechanisms). This allows each component to be optimized independently, with frequency locked through Ethernet and phase/TOD recovered through wireless packet timestamps.
Solution Approach 2:
The patent introduces wireless communication packets as an intermediary carrier that transports timestamp information (including phase and TOD data) between wired networks. These packets serve as the mediator that bridges the gap where synchronous-Ethernet alone cannot distribute phase information over wireless links.
2Loss of information
If IEEE 1588V.2 method is used to distribute clock, then any type of clock information can be distributed, but the system becomes much more sensitive to packet delay variation, packet loss and network behavior
Solution Approach 1:
The patent extracts only the essential timestamp information (phase and TOD) from the full IEEE 1588V.2 protocol and transports it through simplified wireless packets. By taking out only the critical synchronization data rather than implementing the complete protocol stack, the system reduces sensitivity to packet delay and loss while maintaining the ability to distribute all necessary clock information.
Solution Approach 2:
The patent implements partial action by using a simplified version of IEEE 1588V.2 that focuses only on timestamp exchange for phase and TOD synchronization, rather than implementing the full protocol. This partial implementation reduces complexity and sensitivity to network conditions while still achieving the necessary synchronization goals.
3Adaptability or versatility
If wireless link is used to connect wired networks, then connectivity is achieved, but clock synchronicity between wired networks becomes difficult to maintain due to oscillator inaccuracies
Solution Approach 1:
The patent implements feedback mechanisms where wireless communication packets carry timestamp information that allows receiving end devices to measure and compensate for clock drift. By continuously exchanging timing information and adjusting local oscillators based on received timestamps, the system maintains clock synchronicity despite the inherent inaccuracies of wireless transmission and local oscillators.
Solution Approach 2:
The patent dynamically adjusts clock parameters (frequency and phase) based on timestamp measurements from wireless packets. By changing the oscillator parameters in real-time based on received timing information, the system compensates for drift and maintains synchronization across the wireless link connecting the wired networks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively synchronizes clock frequencies across wired networks connected via wireless links, maintaining accuracy despite manufacturing inaccuracies and temperature variations, while being resilient to signal integrity issues and signal drops.
Implementation Method 1
a modulator modulates the data stream using the synthesized clock frequency, resulting in a modulated signal
Implementation Method 2
A clock adder adds the clock frequency error to the reference clock frequency, resulting in a synthesized clock frequency
Data Source
AI summary
A clock extractor extracts clock frequency f2, from a wired data connection. A clock error estimator estimates a first clock frequency error between clock frequency f2 and a clock frequency f1 associated with a local clock of the transmitter. A transmitter sends the first clock frequency error, as a message to a receiver. The transmitter uses a wireless transmitter interface, including a modulator and transmitter radio. The wireless transmitter interface is clocked at clock frequency f1. The transmitter sends data to the receiver. A wireless receiver interface includes a de-modulator and receiver radio. The wireless receiver interface reconstructs clock frequency f1. A clock adder adds the reconstructing clock frequency f1 to the first clock frequency error, resulting in a synthesized clock frequency f2. The receiver clocks a second wired data connection, using the synthesized clock frequency f2.